专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008008546A2 UNIVERSAL RECONFIGURABLE SCAN ARCHITECTURE 审中-公开
标题翻译：通用可重构扫描架构
公开(公告)号：WO2008008546A2
公开(公告)日：2008-01-17
申请号：PCT/US2007/016088
申请日：2007-07-16
申请人： CHEN, Xinghao
发明人： CHEN, Xinghao
IPC分类号： H03M9/00
CPC分类号： G01R31/318536
摘要： A universal reconfigurable scan architecture reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration- set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells. A pulse on the configuration-set (CS) signal triggers PT Hold latches to capture configuration data from corresponding slave latches, which in turn set configurations of each of the reconfigurable scan cells.
摘要翻译：通用可重构扫描架构通过扫描负载操作重新配置扫描结构，从而消除互连网络分配配置信号，并采用与掩模级别相同的公共扫描电路，适用于ASIC实现。该架构包括可重新配置的扫描单元，用于将配置数据分配到可重新配置的扫描单元并且用于确定每个可重构扫描单元的所需重新配置数据以及配置集（CS）信号的装置。每个可重构扫描单元具有直通（PT）模式，其中扫描单元的扫描（SI）或系统数据（SD）的数据输入被透明地传递到扫描输出（ SO）端子，而不需要在移位时钟（SC）上的脉冲。配置集（CS）信号与每个可重构扫描单元进行通信。配置集（CS）信号上的一个脉冲触发PT Hold锁存器，从相应的从锁存器捕获配置数据，依次设置每个可重构扫描单元的配置。

2. 发明申请

WO2008108775A3 DYNAMIC PARTITIONING FOR AREA-EFFICIENT MULTI-PORT MEMORY 审中-公开
公开(公告)号：WO2008108775A3
公开(公告)日：2008-09-12
申请号：PCT/US2007/008542
申请日：2007-04-06
申请人： CHEN, Xinghao , BAJWAR, Hassan
发明人： CHEN, Xinghao , BAJWAR, Hassan
IPC分类号： G11C8/00
摘要： Dynamic partitioning for area-efficient multi-port memory (40) At least one bit-9 line isolation node (52, 54) is placed on bit lines (46, 48) between word line sections (42, 44) and separate a long physical bit line (46, 48) into two virtually and electronically 5 separate sections (66, 70), with one section (66) electronically connected to an upper port (64) and the other section (70) electronically connected to a lower port (68) to shorten effective bit lines physically connected to a port (64, 68) At least one isolation control line (50), each of which controls the bit-line isolation nodes (52, 54) separating same word line sections (42, 44) At least one dynamic memory partition control circuit (51) has outputs feeding corresponding isolation control lines (50)

3. 发明申请

WO2007143220A3 RECONFIGURABLE SCAN ARRAY STRUCTURE 审中-公开
公开(公告)号：WO2007143220A3
公开(公告)日：2007-12-13
申请号：PCT/US2007/013428
申请日：2007-06-07
申请人： CHEN, Xinghao
发明人： CHEN, Xinghao
IPC分类号： G01R31/28
摘要： A reconfigurable scan array structure (60) for providing greater flexibility in customizing scan configurations for post-manufacturing applications. The structure (60) includes multiple scan cell segments (62), programmable scan-mode control switches (66), and programmable scan configuration switches (72). The multiple scan cell segments (62) are arranged in an array (64). The programmable scan-mode control switches (66) are placed between same scan cells (68) on two neighboring scan cell segments (70) and enable fine-tuning custom scan configurations to maximize effectiveness and efficiency for individual applications and designs. The programmable scan configuration switches (72) are placed between two scan cell segments (62) on a same row (74) as well as the left and right sides (76,78) of the scan array structure (60) and provide access points into the array structure (60) by SIs, SOs, or MISRs, and other manufacturing-critical components as well as enabling many scan configurations.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式