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1. 发明申请

WO0165765A3 METHOD AND DEVICE FOR DISTRIBUTING BANDWIDTH 审中-公开
标题翻译：用于分布带宽的方法和装置
公开(公告)号：WO0165765A3
公开(公告)日：2002-03-07
申请号：PCT/US0100874
申请日：2001-01-11
申请人： CELOX NETWORKS INC , HEGDE MANJU , SCHMID OTTO ANDREAS , BORDES JEAN PIERRE , ZHAO XINGGUO , MAHER MONIER , DAVIS CURTIS
发明人： HEGDE MANJU , SCHMID OTTO ANDREAS , BORDES JEAN PIERRE , ZHAO XINGGUO , MAHER MONIER , DAVIS CURTIS
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/44
CPC分类号： H04L49/3081 , H04L12/5601 , H04L47/10 , H04L47/39 , H04L2012/5632 , H04Q11/0478
摘要： A method and device for controlling bandwidth distribution through a switch fabric is provided wherein a plurality of line cards and processor cards are connected through a switch fabric for parallel processing of transmission requests, along with the provision of transmission "credits" allowing for transmitting additional data bytes during a given cycle, which provides efficient and speedy bandwidth distribution, as well as resolution of output contentions. The processors maintain a credit balance which allows flexibility in granting transmission requests to accommodate transmission scheduling and "bursty" transmissions. Processors on both of the line cards and the processor cards normalize the data transmission requirements for both inputs and outputs connected by the switch fabric. Smoothing of data transmission is provided using a time-weighted buffer.
摘要翻译：提供一种用于控制通过交换结构的带宽分配的方法和装置，其中通过交换结构连接多个线路卡和处理器卡，用于并行处理传输请求，以及提供允许发送附加数据的传输“信用” 字节在给定的周期，提供有效和快速的带宽分布，以及输出争用的分辨率。处理器保持信用余额，允许灵活地授予传输请求以适应传输调度和“突发”传输。两个线卡和处理器卡上的处理器标准化了由交换结构连接的输入和输出的数据传输要求。使用时间加权缓冲器提供数据传输的平滑。

2. 发明申请

WO0156327A9 DEVICE AND METHOD FOR PACKET INSPECTION 审中-公开
标题翻译：分组检查的装置和方法
公开(公告)号：WO0156327A9
公开(公告)日：2001-11-08
申请号：PCT/US0101002
申请日：2001-01-11
申请人： CELOX NETWORKS INC , MAHER MONIER , SCHMID OTTO ANDREAS , BORDES JEAN PIERRE , HEGDE MANJU , DAVIS CURTIS
发明人： MAHER MONIER , SCHMID OTTO ANDREAS , BORDES JEAN PIERRE , HEGDE MANJU , DAVIS CURTIS
IPC分类号： H04L12/54 , H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04Q11/0478 , H04L12/56 , H04L2012/5667
摘要： A method and device for packet inspection whereby packets presented via an interleaved cell stream can be inspected "on the fly" to identify, for example, the sequence of protocol encapsulations for each packet, as well as those portions of the packet which should be captured. The packet inspector is therefore capable of operating at high speeds. The packet inspector can also be used to inspect the payload portion of packets, if desired. A connection table look-up unit is used that accesses connection-based control data from a connection table for each cell input to the packet inspector. The look-up unit forwards the cell-specific control data to a data inspector via a forward control path, and the data inspector uses this control data when processing the associated cell. When processing of that cell is complete, the data inspector updates the associated control data to summarize its findings thus far, and then sends the updated control data back towards the look-up unit via a reverse control path for storage. When the next cell of the same packet is presented to the packet processor, the look-up unit retrieves and forwards the stored control data, which the data inspector uses to resumes the packet inspection process. A mechanism is also provided for replacing the control data for a cell propagating on the forward control path with updated control data that is propagating on the reverse control path.
摘要翻译：用于分组检查的方法和装置，其中可以“即时”检查经由交织的小区流所呈现的分组，以识别例如每个分组的协议封装的序列以及应该被捕获的分组的那些部分。因此，数据包检查器能够以高速运行。如果需要，分组检查器也可以用于检查分组的有效载荷部分。使用连接表查找单元，该连接表查找单元从连接表访问基于连接的每个单元输入到分组检查器的控制数据。查找单元经由前向控制路径将小区特定控制数据转发到数据检查器，并且当处理相关联的小区时，数据检查器使用该控制数据。当该单元的处理完成时，数据检查器更新关联的控制数据以总结其到目前为止的发现，然后经由反向控制路径将更新的控制数据发送回查找单元用于存储。当相同分组的下一个小区被呈现给分组处理器时，查找单元检索并转发存储的控制数据，数据检查器使用该控制数据来恢复分组检查过程。还提供了一种机制，用于用在反向控制路径上传播的更新的控制数据来替换在前向控制路径上传播的单元的控制数据。

3. 发明申请

WO0167694A9 BROADBAND MID-NETWORK SERVER 审中-公开
标题翻译：宽带中间网络服务器
公开(公告)号：WO0167694A9
公开(公告)日：2002-01-10
申请号：PCT/US0101003
申请日：2001-01-11
申请人： CELOX NETWORKS INC , BORDES JEAN PIERRE , SCHMID OTTO ANDREAS , DAVIS CURTIS , MAHER MONIER , HEGDE MANJU
发明人： BORDES JEAN PIERRE , SCHMID OTTO ANDREAS , DAVIS CURTIS , MAHER MONIER , HEGDE MANJU
IPC分类号： H04L12/70 , H04L12/931 , H04L12/935 , H04L12/937 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/3009 , H04L49/205 , H04L49/255 , H04L49/30 , H04L49/3081 , H04L49/351 , H04L49/40 , H04L49/503 , H04L49/602 , H04L49/608 , H04L2012/5667 , H04Q11/0478
摘要： A broadband mid-network server provides high-speed, reliable, secure, flexible, high-bandwidth, and easily managed access to the Internet to accommodate all current Internet services including email, file transfer, web surfing and e-commerce, as well as new value added services such as VoIP and Real Time Video. The preferred server is scalable in terms of both bandwidth and processing power. The server includes the ability to distribute traffic across a number of Internet processing engines and, more specifically, across a number of protocol processing units provided in each engine (the bandwidth to which can be coordinated), to provide compute power and state space required for performing per user processing for a large number of users.
摘要翻译：宽带中型网络服务器提供高速，可靠，安全，灵活，高带宽和易于管理的互联网访问，以适应当前所有的互联网服务，包括电子邮件，文件传输，网络冲浪和电子商务，以及新的增值服务，如VoIP和实时视频。首选服务器在带宽和处理能力方面都是可扩展的。服务器包括跨多个因特网处理引擎分配流量的能力，更具体地说，跨越每个引擎中提供的多个协议处理单元（可协调的带宽）来提供计算能力和状态空间针对大量用户执行每个用户处理。

4. 发明申请

WO2005038559A3 PHYSICS PROCESSING UNIT 审中-公开
标题翻译：物理处理单元
公开(公告)号：WO2005038559A3
公开(公告)日：2006-03-16
申请号：PCT/US2004030686
申请日：2004-09-20
申请人： AGEIA TECHNOLOGIES INC , DAVIS CURTIS , HEGDE MANJU , SCHMID OTTO A , MAHER MONIER , BORDES JEAN PIERRE
发明人： DAVIS CURTIS , HEGDE MANJU , SCHMID OTTO A , MAHER MONIER , BORDES JEAN PIERRE
IPC分类号： G06F20060101 , G06F17/10 , G06F19/00
CPC分类号： G06T1/20
摘要： A High-speed data Bus (HSB) (48) together with a Memory Interface Unit (M 1 U) (50) form the connection between the PPU and an external high-speed memory (not shown). DME (18) and FPE (19) provide the high-speed computational platform necessary to provide complex, real-time physics simulation data. In order to access external memory, as managed by MIU (50), processor bus (44) issues read/write requests to bridge (47) connecting processor bus (44) with HSB (48).
摘要翻译：高速数据总线（HSB）（48）与存储器接口单元（M 1 U）（50）一起形成PPU和外部高速存储器（未示出）之间的连接。 DME（18）和FPE（19）提供了提供复杂的实时物理模拟数据所需的高速计算平台。为了访问由MIU（50）管理的外部存储器，处理器总线（44）发出将连接处理器总线（44）与HSB（48）桥接（47）的读/写请求。

5. 发明申请

WO2005038560A3 METHOD FOR PROVIDING PHYSICS SIMULATION DATA 审中-公开
标题翻译：提供物理模拟数据的方法
公开(公告)号：WO2005038560A3
公开(公告)日：2006-05-18
申请号：PCT/US2004030687
申请日：2004-09-20
申请人： AGEIA TECHNOLOGIES INC , DAVIS CURTIS , HEGDE MANJU , SCHMID OTTO A , MAHER MONIER , BORDES JEAN PIERRE
发明人： DAVIS CURTIS , HEGDE MANJU , SCHMID OTTO A , MAHER MONIER , BORDES JEAN PIERRE
IPC分类号： A63F13/00 , A63F13/10 , G06F20060101 , A63F9/24 , G06F17/00 , G06F19/00
CPC分类号： G06F15/80 , A63F13/10 , A63F13/577 , A63F2300/6018 , A63F2300/64
摘要： A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.
摘要翻译：一种在游戏程序或模拟中提供物理数据的方法，其使用具有唯一架构的基于硬件的物理处理单元，其被设计为有效地计算物理相关数据。

6. 发明申请

WO2005038561A2 SYSTEM INCORPORATING PHYSICS PROCESSING UNIT 审中-公开
标题翻译：系统加工物理处理单元
公开(公告)号：WO2005038561A2
公开(公告)日：2005-04-28
申请号：PCT/US2004030689
申请日：2004-09-20
申请人： AGEIA TECHNOLOGIES INC , DAVIS CURTIS , HEGDE MANJU , SCHMID OTTO A , MAHER MONIER , BORDES JEAN PIERRE
发明人： DAVIS CURTIS , HEGDE MANJU , SCHMID OTTO A , MAHER MONIER , BORDES JEAN PIERRE
IPC分类号： G06F20060101 , G06F9/45 , G06F
CPC分类号： G06F15/80 , A63F13/10 , A63F2300/6063 , A63F2300/64 , A63F2300/643 , G06T1/20
摘要： A system, such as a PC, incorporating a dedicated physics processing unit adapted to generate physics data for use within a physics simulation or game animation. The hardware-based physics processing unit is characterized by a unique architecture designed to efficiently calculate physics data, including multiple, parallel floating point operations.
摘要翻译：一种诸如PC的系统，其包括专用物理处理单元，其适于产生用于物理学模拟或游戏动画内的物理数据。基于硬件的物理处理单元的特征在于独特的架构，旨在有效地计算物理数据，包括多个并行浮点运算。

7. 发明申请

WO2006055279A3 SYSTEM WITH PPU/GPU ARCHITECTURE 审中-公开
标题翻译：系统与PPU / GPU架构
公开(公告)号：WO2006055279A3
公开(公告)日：2007-11-08
申请号：PCT/US2005040007
申请日：2005-11-03
申请人： AGEIA TECHNOLOGIES INC , BORDES JEAN PIERRE , DAVIS CURTIS , HEDGE MANJU
发明人： BORDES JEAN PIERRE , DAVIS CURTIS , HEDGE MANJU
IPC分类号： A61F13/00 , G06F17/00
CPC分类号： G06F15/7864
摘要： A PPU-enhanced system is described in which a Physics Processing Unit (PPU) (44) and a Graphics Processing Unit (GPU) (40) are connected with the system.
摘要翻译：描述了一种PPU增强系统，其中物理处理单元（PPU）（44）和图形处理单元（GPU）（40）与系统连接。

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