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1. 发明申请

WO2007074056A3 ERROR-TOLERANT PROCESSOR SYSTEM 审中-公开
标题翻译： ERROR PEACE处理器系统
公开(公告)号：WO2007074056A3
公开(公告)日：2007-12-06
申请号：PCT/EP2006069610
申请日：2006-12-12
申请人： BOSCH GMBH ROBERT , HARTER WERNER , KOTTKE THOMAS , COLLANI YORCK , EL SALLOUM CHRISTIAN
发明人： HARTER WERNER , KOTTKE THOMAS , COLLANI YORCK , EL SALLOUM CHRISTIAN
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0721 , G06F11/0739 , G06F11/0757 , G06F11/0766 , G06F11/1008
摘要： Disclosed is a processor system comprising at least one execution unit (1) for executing program instructions of an application, a program memory (3) for storing program instructions of the application and at least one error recovery routine, a main memory (2) for storing a set of variables of the application, and or a monitoring unit (10) for detecting errors of the execution unit (1) and/or the main memory (2, 7, 8) and starting an error recovery routine in case an error is detected. The error recovery routines are designed such that each error recovery routine restores different subsets of the set of variables.
摘要翻译：一种处理器系统，包括至少一个执行单元（1），用于执行应用程序的程序指令，程序存储器（3），用于存储应用程序的程序指令和至少一个错误处理例程，用于存储一组的应用程序和一个监视单元的变量的工作存储器（2）（10 ），用于检测执行单元（1）和/或存储器（2,7的错误，8）和启动的错误在检测到错误的情况下，处理例程。错误处理程序旨在更新组变量的每个不同的子集。

2. 发明申请

WO2006045755A3 METHOD AND DEVICE FOR INCREASING THE AVAILABILITY OF A MEMORY UNIT AND MEMORY UNIT 审中-公开
标题翻译：方法和设备用于增加存储单元和存储单元的可用性
公开(公告)号：WO2006045755A3
公开(公告)日：2006-07-27
申请号：PCT/EP2005055438
申请日：2005-10-20
申请人： BOSCH GMBH ROBERT , WEIBERLE REINHARD , MUELLER BERND , HARTER WERNER , ANGERBAUER RALF , KOTTKE THOMAS , COLLANI YORCK , GMEHLICH RAINER , PFEIFFER WOLFGANG , HARTWICH FLORIAN , GRAEBITZ KARSTEN
发明人： WEIBERLE REINHARD , MUELLER BERND , HARTER WERNER , ANGERBAUER RALF , KOTTKE THOMAS , COLLANI YORCK , GMEHLICH RAINER , PFEIFFER WOLFGANG , HARTWICH FLORIAN , GRAEBITZ KARSTEN
IPC分类号： G06F12/08 , G11C29/00
CPC分类号： G06F11/1064 , G06F12/0802 , G11C29/88
摘要： The invention relates to a method and to a device for increasing the availability, after an error recognition in a volatile memory unit, in particular a cache memory. Access to the data and/or instructions stored in the volatile memory unit takes place by means of said addresses associated therewith, and data and/or instructions identified as defective are blanked out, and the addresses associated with said data and/or instructions are no longer used.
摘要翻译：一种用于在易失性存储器单元的情况下，故障检测后增加的可用性的方法和设备，尤其是高速缓冲存储器，所述访问所述非易失性存储器单元是通过用相关联，并识别为有错误的数据和/或指令被隐藏这些地址存储的数据和/或指令由该信息和/或分配的指令的地址是不再使用。

3. 发明申请

WO2006045782A3 METHOD AND DEVICE FOR SWITCHING BETWEEN OPERATING MODES OF A MULTIPROCESSOR SYSTEM BY MEANS OF AT LEAST ONE EXTERNAL SIGNAL 审中-公开
标题翻译：方法和装置切换之间的多处理器系统的工作模式由至少一个外部信号
公开(公告)号：WO2006045782A3
公开(公告)日：2007-01-04
申请号：PCT/EP2005055509
申请日：2005-10-25
申请人： BOSCH GMBH ROBERT , WEIBERLE REINHARD , MUELLER BERND , ANGERBAUER RALF , COLLANI YORCK , GMEHLICH RAINER , BOEHL EBERHARD , KOTTKE THOMAS , PFEIFFER WOLFGANG , HARTWICH FLORIAN , HARTER WERNER , GRAEBITZ KARSTEN
发明人： WEIBERLE REINHARD , MUELLER BERND , ANGERBAUER RALF , COLLANI YORCK , GMEHLICH RAINER , BOEHL EBERHARD , KOTTKE THOMAS , PFEIFFER WOLFGANG , HARTWICH FLORIAN , HARTER WERNER , GRAEBITZ KARSTEN
IPC分类号： G06F9/38
CPC分类号： G06F11/1641 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F2201/845
摘要： The invention relates to a method for switching in a computer system comprising at least two execution units (110a, 110b). It is possible to switch between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. The invention is characterised in that the switching is triggered by at least one signal (160) generated outside the computer system.
摘要翻译：至少两个工作模式之间切换的在具有至少两个执行单元（110A，110B）的计算机系统中进行切换的方法，和第一操作模式到一个比较模式和第二操作模式到高性能模式对应，其特征在于（160）触发的至少一个信号的开关在计算机系统的外部产生。

4. 发明申请

WO2006015945A3 METHOD, OPERATING SYSTEM, AND COMPUTING DEVICE FOR PROCESSING A COMPUTER PROGRAM 审中-公开
标题翻译：用于编辑计算机程序的程序，操作系统和控制装置
公开(公告)号：WO2006015945A3
公开(公告)日：2006-06-08
申请号：PCT/EP2005053621
申请日：2005-07-25
申请人： BOSCH GMBH ROBERT , WEIBERLE REINHARD , MUELLER BERND , HARTER WERNER , KOTTKE THOMAS , COLLANI YORCK , GMEHLICH RAINER
发明人： WEIBERLE REINHARD , MUELLER BERND , HARTER WERNER , KOTTKE THOMAS , COLLANI YORCK , GMEHLICH RAINER
IPC分类号： G06F11/14
CPC分类号： G06F11/1438 , G06F11/1479
摘要： The invention relates to a method for processing a computer program (23) on a computing device (20), particularly a microprocessor (22). Said computer program (23) comprises several program objects that are configured as tasks, for example. Transient and permanent errors are detected during the time the computer program (23) is processed on the computing device (20). In order to be able to constructively treat transient errors when the same occur in a computer system such that the operability and the operational safety of the computer system are reestablished within the shortest possible error tolerance interval, a program object that has already been fed for processing is converted into a defined state and is restarted from said defined state when an error is detected. Said program object represents a run time object of the computer program, a task, for example. According to the inventive method, one or several tasks which continue to be processed or have already been processed when the error occurs can be restarted and executed.
摘要翻译：本发明涉及一种用于在计算设备（20）上，特别是在微处理器（22）上处理计算机程序（23）的方法。计算机程序（23）包括例如被设计为任务的多个程序对象。在处理计算设备（20）上的计算机程序（23）期间，检测到瞬态和永久性错误。为了能够以这样的建设性地在计算机系统中的瞬态错误的事件来处理这些，该计算机系统的可操作性和可靠性是在很短的尽可能容错时间重新建立，提出的是，对于检测到错误中的至少一个程序对象已处理被提供，转移到一个确定的状态并从此重新启动。程序对象例如是计算机程序（23）的运行时对象，即所谓的任务。为了本发明的目的，当错误发生或者已经被执行时仍然执行的一个任务或者多个任务可以被重新启动并且被执行。

5. 发明申请

WO2006045733A2 METHOD, OPERATING SYSTEM AND COMPUTING ELEMENT FOR RUNNING A COMPUTER PROGRAM 审中-公开
标题翻译：方法，操作系统和计算设备执行的计算机程序
公开(公告)号：WO2006045733A2
公开(公告)日：2006-05-04
申请号：PCT/EP2005055390
申请日：2005-10-19
申请人： BOSCH GMBH ROBERT , WEIBERLE REINHARD , MUELLER BERND , HARTER WERNER , ANGERBAUER RALF , KOTTKE THOMAS , COLLANI YORCK , GMEHLICH RAINER
发明人： WEIBERLE REINHARD , MUELLER BERND , HARTER WERNER , ANGERBAUER RALF , KOTTKE THOMAS , COLLANI YORCK , GMEHLICH RAINER
CPC分类号： G06F11/1438
摘要： The invention relates to a method for running a computer program on a computing element, particularly on a microprocessor. The computer program has a number of program objects, and over the course of the method, errors are detected while running the computer program on the computing element. When an error is detected, at least one program object that has already been run is transferred into a defined state and restarted from this state, and subsequent additional program objects are postponed.
摘要翻译：本发明涉及一种用于在微处理器上，其中所述计算机程序包括多个在所述计算设备的故障的计算机程序的执行期间的方法的程序对象并在计算机上执行的计算机程序，尤其是处理的方法进行检测，在检测的误差中的至少一个程序对象已经被提供给执行，转移到所定义的状态，并再次开始的这一点，以及随后的进一步的程序对象被移动。

6. 发明申请

WO2006015955A3 METHOD FOR REGISTERING ERRORS AND CORRESPONDING REGISTER 审中-公开
标题翻译：方法错误注册及相应的寄存器
公开(公告)号：WO2006015955A3
公开(公告)日：2006-06-08
申请号：PCT/EP2005053730
申请日：2005-08-01
申请人： BOSCH GMBH ROBERT , KOTTKE THOMAS , STEININGER ANDREAS , EL SALLOUM CHRISTIAN
发明人： KOTTKE THOMAS , STEININGER ANDREAS , EL SALLOUM CHRISTIAN
IPC分类号： G06F11/07
CPC分类号： G06F11/1679 , G06F11/0739 , G06F11/0772 , G06F11/0793 , G06F11/0796 , G06F2201/845
摘要： The invention relates to a method for registering errors and to a register which is associated with a dual calculating system. Information in the form of bits is stored in the register and the dual calculating system contains an error recognising mechanism, whereby the bits in the register represent at least one error signal of the error recognition mechanism as an error bit.
摘要翻译：一种用于错误注册方法和注册其与双处理器系统，其中，存储在比特的形式，其中所述的双处理器系统包括一个错误检测机制寄存器信息相关联，其中表示错误检测机构的在寄存器中的至少错误比特的误差信号的位。

7. 发明申请

WO2006045807A2 DATA PROCESSING SYSTEM WITH A VARIABLE CLOCK SPEED 审中-公开
标题翻译：具有可变中风发生率数据处理系统
公开(公告)号：WO2006045807A2
公开(公告)日：2006-05-04
申请号：PCT/EP2005055549
申请日：2005-10-25
申请人： BOSCH GMBH ROBERT , COLLANI YORCK , KOTTKE THOMAS
发明人： COLLANI YORCK , KOTTKE THOMAS
CPC分类号： G06F1/324 , G06F9/30181 , G06F9/3851 , G06F11/0757 , G06F11/1641 , G06F11/1695 , Y02D10/126
摘要： A data processing system comprises an execution unit (1) that functions in a clocked manner, a clock generator (5) for supplying a clock signal for the execution unit (1), and a monitoring unit (3) for monitoring the proper functioning of the execution unit (1). The clock generator (5) is designed for supplying the clock signal with a controllable frequency. The monitoring unit (3) is functionally connected to the clock generator (5) in order to lower the frequency of the clock signal when it has been established that the execution unit (1) is functioning improperly.
摘要翻译：一种数据处理系统包括一个时钟操作执行单元（1），用于执行单元（1）和一个监视单元提供时钟信号的时钟发生器（5）（3），用于监测所述执行单元的正确操作（1）。时钟生成器（5）被设置成提供具有可控频率的时钟信号。监控单元（3）可操作地连接到时钟生成器（5）检测到执行单元（1）的不正确操作时，降低时钟信号的频率。

8. 发明申请

WO2007025816A3 MEMORY ARRANGEMENT AND METHOD FOR THE OPERATION THEREOF 审中-公开
标题翻译：存储安排和操作方法
公开(公告)号：WO2007025816A3
公开(公告)日：2007-05-24
申请号：PCT/EP2006064768
申请日：2006-07-28
申请人： BOSCH GMBH ROBERT , KOTTKE THOMAS , COLLANI YORCK , FERCH MARKUS
发明人： KOTTKE THOMAS , COLLANI YORCK , FERCH MARKUS
IPC分类号： G06F11/10
CPC分类号： G06F11/1008
摘要： The invention relates to a memory arrangement which comprises a writable data memory (102) and means for recognising (103) an error in a data word, which is read from the data memory (102), and for correcting (101) the error and saving (101) the corrected data word to a new address in a free area of the data memory (102).
摘要翻译：一种存储器阵列，其包括可记录数据存储（102），以及用于检测从所述数据存储器（102）的数据字读入（103）的误差在校正（101）的误差，并存储（101）校正后的数据字到一个新的地址数据存储器（102）的空闲区域。

9. 发明申请

WO2006015964A3 METHOD FOR DELAYING ACCESS TO DATA AND/OR COMMANDS OF A DUAL COMPUTER SYSTEM, AND CORRESPONDING DELAYING UNIT 审中-公开
标题翻译：方法DEFER访问数据和/或两个计算机系统的命令和相关延迟单元
公开(公告)号：WO2006015964A3
公开(公告)日：2006-05-11
申请号：PCT/EP2005053791
申请日：2005-08-03
申请人： BOSCH GMBH ROBERT , MUELLER BERND , HARTER WERNER , KOTTKE THOMAS , STEININGER ANDREAS
发明人： MUELLER BERND , HARTER WERNER , KOTTKE THOMAS , STEININGER ANDREAS
IPC分类号： G06F11/16
CPC分类号： G06F11/1641 , G06F11/1679 , G06F11/1695 , G06F2201/845
摘要： Disclosed are a delaying unit (102) and a method for delaying access to data and/or commands of a dual computer system comprising a first (100) and a second computer (101), the first computer operating in a time-deferred manner relative to the second computer. The delaying unit is configured such that the deferral in the dual computer system is compensated in at least one of the two computers when data and/or commands are accessed. Also disclosed are a method and a delaying unit for delaying access to data and/or commands of a computer system comprising error detection mechanisms. Said method and delaying unit are characterized in that the time lapsing between undelayed access to data and/or commands and the detection of an error is compensated.
摘要翻译：延迟单元（102）和方法，用于延迟所述访问数据和/或双重计算机系统，包括第一（100）和第二计算机（101），其中，所述第一部分相对于第二计算机有一个时间差和延迟单元进行操作的命令被适配这个时间延迟在访问数据在两主机系统补偿和/或命令，以及方法和延迟单元来延迟对数据的访问和/或计算机系统以用于检错的错误检测机制的命令，其特征在于一个非延迟访问之间的持续时间的数据和 /或指令，和检错被补偿。

10. 发明申请

WO2006045801A2 METHOD AND DEVICE FOR MONITORING A MEMORY UNIT IN A MULTI-PROCESSOR SYSTEM 审中-公开
标题翻译：用于在多处理器系统中监视存储单元的方法和设备
公开(公告)号：WO2006045801A2
公开(公告)日：2006-05-04
申请号：PCT/EP2005055538
申请日：2005-10-25
申请人： BOSCH GMBH ROBERT , KOTTKE THOMAS , TRITTLER STEFAN
发明人： KOTTKE THOMAS , TRITTLER STEFAN
CPC分类号： G06F11/1695 , G06F9/30189 , G06F9/3851 , G06F9/3885 , G06F11/1641 , G06F2201/845
摘要： The invention relates to a method and to a device for monitoring a memory unit in a system comprising at least two computing units and switching means used for switching switched between at least two operational modes. The device is embodied such that the contents of the memory unit and/or the operation mode, wherein the memory unit is contained, are created by logging.
摘要翻译：用于与至少两个处理单元，通过该监视的存储单元的系统中的方法和装置可以在系统，其中所述设备被配置成使得至少两个工作模式之间，所述存储器的内容和/或操作模式的记录操作被执行，其中，切换装置被包括在被切换内存内容已创建。

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