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1. 发明申请

WO2008153777A2 LOW COST AND LOW VARIATION OSCILLATOR 审中-公开
标题翻译：低成本和低变化振荡器
公开(公告)号：WO2008153777A2
公开(公告)日：2008-12-18
申请号：PCT/US2008/006664
申请日：2008-05-23
申请人： ATMEL CORPORATION , FORT, Jimmy , CUENCA, Michel , PAYRARD, Daniel
发明人： FORT, Jimmy , CUENCA, Michel , PAYRARD, Daniel
IPC分类号： H03K3/03 , H03K3/354
CPC分类号： H03K3/354 , H03K3/011 , H03K3/0231 , H03K5/133 , H03K5/1565 , H03K2005/0013 , H03K2005/00143 , H03K2005/00202
摘要： An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.
摘要翻译：用于集成电路的振荡电路。所述振荡器电路包括具有至少第一电流镜分支和第二电流镜分支的电流镜的延迟产生电路，耦合到所述第一电流镜分支的电流源，耦合到所述第一电流镜分支的电容元件; 以及耦合到第二电流镜分支的电阻元件。振荡器电路还包括彼此串联耦合的多个反相元件和耦合到多个反相元件的输出的跨导元件。跨导元件被配置为放电电容元件。锁存元件被耦合以锁存到多个反相元件的输出信号。

2. 发明申请

WO2008153781A1 LOW VOLTAGE CHARGE PUMP 审中-公开
标题翻译：低电压充电泵
公开(公告)号：WO2008153781A1
公开(公告)日：2008-12-18
申请号：PCT/US2008/006669
申请日：2008-05-23
申请人： ATMEL CORPORATION , FORT, Jimmy , SIRACUSA, Fabrice
发明人： FORT, Jimmy , SIRACUSA, Fabrice
IPC分类号： H02M3/07
CPC分类号： H02M3/073 , H02M2003/075
摘要： A single pump stage (200) of a multi-stage charge pump couples a first low-voltage NMOS transistor (N1) in series with a first low-voltage PMOS transistor (P1) between charge transfer capacitors (Ct1, Ct2). A second low- voltage NMOS transistor (N2) is coupled between the gate and the source of the first NMOS transistor (N1). A second low-voltage PMOS transistor (P2) is coupled between the gate and the source of the first PMOS transistor (P1). Respective boost voltages are applied to gates of the first NMOS transistor (N1) and the first PMOS transistor (P1) to minimize threshold voltage losses. A stabilizing capacitor (Ci) is connected between the first NMOS transistor (N1) and the first PMOS transistor (P1).
摘要翻译：多级电荷泵的单个泵级（200）将第一低电压NMOS晶体管（N1）与电荷转移电容器（Ct1，Ct2）之间的第一低电压PMOS晶体管（P1）串联耦合。第二低电压NMOS晶体管（N2）耦合在第一NMOS晶体管（N1）的栅极和源极之间。第二低电压PMOS晶体管（P2）耦合在第一PMOS晶体管（P1）的栅极和源极之间。相应的升压电压施加到第一NMOS晶体管（N1）和第一PMOS晶体管（P1）的栅极，以最小化阈值电压损耗。稳定电容器（Ci）连接在第一NMOS晶体管（N1）和第一PMOS晶体管（P1）之间。

3. 发明申请

WO2008100428A1 SINGLE ENDED SENSE AMPLIFIER 审中-公开
标题翻译：单端感应放大器
公开(公告)号：WO2008100428A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/001696
申请日：2008-02-08
申请人： ATMEL CORPORATION , FORT, Jimmy
发明人： FORT, Jimmy
IPC分类号： G11C7/06
CPC分类号： G11C7/067
摘要： A sense amplifier has a transimpedance amplifier capable of producing an output voltage level proportionate to a current variation sensed going into a bitline. A transconductance device is configured to produce varying bitline current in response to the transimpedance amplifier output voltage. The transconductance device is capable of utilizing the transimpedance amplifier output voltage as feedback to produce a bitline clamp voltage level. The transimpedance amplifier configured to produce an output voltage proportionate to a cell current of a selected memory cell and provide an output signal corresponding to a memory cell state. An output amplifier is coupled to the transimpedance amplifier and capable of producing an output signal level proportionate to the transimpedance amplifier output voltage. A bias circuit is coupled to the transimpedance amplifier and the output amplifier, the bias circuit is capable of producing reference mirror currents through the transimpedance amplifier and the output amplifier.
摘要翻译：读出放大器具有跨阻抗放大器，能够产生与感测进入位线的电流变化成比例的输出电压电平。跨导装置被配置为响应于跨阻放大器输出电压产生变化的位线电流。跨导器件能够利用跨阻放大器输出电压作为反馈来产生位线钳位电压电平。跨阻放大器被配置为产生与所选择的存储器单元的单元电流成比例的输出电压，并提供对应于存储单元状态的输出信号。输出放大器耦合到跨阻放大器，并且能够产生与跨阻放大器输出电压成比例的输出信号电平。偏置电路耦合到跨阻放大器和输出放大器，偏置电路能够通过跨阻放大器和输出放大器产生参考反射镜电流。

4. 发明申请

WO2008021655A2 HIGH-SPEED, SELF-SYNCHRONIZED CURRENT SENSE AMPLIFIER 审中-公开
标题翻译：高速，自同步电流检测放大器
公开(公告)号：WO2008021655A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/074009
申请日：2007-07-20
申请人： ATMEL CORPORATION , FORT, Jimmy , DAGA, Jean-michel
发明人： FORT, Jimmy , DAGA, Jean-michel
IPC分类号： G11C7/00
CPC分类号： G11C7/067 , G11C7/14 , G11C16/26 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit (10) and a method for reading a memory cell. A circuit comprises a bit line (46) associated with a memory cell. A first input of a latch (12) is coupled to the bit line and a second input of the latch is coupled to a second node (32) of a dummy bit line (48). There is a means for biasing (24, 26, 38, 40) the first input and the second input of the latch to a differential voltage between the first node (30) coupled to the bit line and the second node. There is also a means for switching (52, 54, 56, 78) the latch according to memory cell current. There is also a means (74, 66, 68) for producing an output signal (dout) indicating the direction of switch. A method of reading a memory cell comprises precharging a bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the bit line and a second node. The latch circuitry is then activated and the latch circuitry switches according to the memory cell current. An output signal indicating the direction of the latch circuitry's switch is then produced.
摘要翻译：一种读出放大器电路（10）和一种用于读取存储单元的方法。电路包括与存储器单元相关联的位线（46）。锁存器（12）的第一输入端耦合到位线，并且锁存器的第二输入端耦合到虚拟位线（48）的第二节点（32）。存在用于将第一输入和锁存器的第二输入偏置（24,26,38,40）到耦合到位线和第二节点的第一节点（30）之间的差分电压的装置。还存在根据存储器单元电流来切换（52,54,56,78）锁存器的装置。还有一种用于产生指示切换方向的输出信号（dout）的装置（74,66,68）。读取存储器单元的方法包括对与存储器单元相关联的位线进行预充电。根据存储单元的编程状态来驱动存储单元电流。锁存电路基于耦合到位线的第一节点与第二节点之间的差分电压而偏置。然后锁存电路被激活，并且锁存电路根据存储单元电流进行切换。然后产生指示锁存电路的开关方向的输出信号。

5. 发明申请

WO2008021108A2 APPARATUS AND METHOD FOR CHARGE PUMP SLEW RATE CONTROL 审中-公开
标题翻译：充电泵转速控制装置和方法
公开(公告)号：WO2008021108A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/017584
申请日：2007-08-08
申请人： ATMEL CORPORATION , FORT, Jimmy , DAGA, Jean-Michel
发明人： FORT, Jimmy , DAGA, Jean-Michel
IPC分类号： H03K5/12
CPC分类号： H03K5/01
摘要： An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.
摘要翻译：公开了一种用于提高存储单元可靠性的装置和方法。当检测到福勒 - 诺德海姆（FN）隧道注入时，用于编程存储单元的施加电压信号中的转换速率降低。所施加的编程信号由电荷泵提供，该电荷泵优选是调节的电荷泵。当电压电平检测电路在预定阈值电压电平检测到FN隧道注入时，电荷泵由转换速率控制电路选择性地控制。

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