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1. 发明申请

WO2019211610A1 HIGH-PERFORMANCE STREAMING OF ORDERED WRITE STASHES TO ENABLE OPTIMIZED DATA SHARING BETWEEN I/O MASTERS AND CPUs 审中-公开
公开(公告)号：WO2019211610A1
公开(公告)日：2019-11-07
申请号：PCT/GB2019/051216
申请日：2019-05-02
申请人： ARM LIMITED
发明人： JALAL, Jamshed , RINGE, Tushar P , TUMMALA, Ashok Kumar , RAMAGIRI, Gurunath
IPC分类号： G06F13/38 , G06F12/0813
摘要： A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

2. 发明申请

WO2021250371A1 AN APPARATUS AND METHOD FOR HANDLING MEMORY ACCESS REQUESTS 审中-公开
公开(公告)号：WO2021250371A1
公开(公告)日：2021-12-16
申请号：PCT/GB2021/051223
申请日：2021-05-20
申请人： ARM LIMITED
发明人： JALAL, Jamshed , RAMAGIRI, Gurunath , RINGE, Tushar P. , WERKHEISER, Mark David , TUMMALA, Ashok Kumar , KASERIDIS, Dimitrios
IPC分类号： G06F13/16 , G06F13/1626 , G06F13/1657
摘要： A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The plurality of requester elements are arranged to issue memory access requests for processing by the plurality of slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by the plurality of requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided that, in response to receipt by the intermediate element of a given memory access request, is arranged to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element. Such an approach can improve overall system bandwidth utilisation.

3. 发明申请

WO2021094704A1 AN APPARATUS AND METHOD FOR HANDLING ORDERED TRANSACTIONS 审中-公开
公开(公告)号：WO2021094704A1
公开(公告)日：2021-05-20
申请号：PCT/GB2020/052281
申请日：2020-09-21
申请人： ARM LIMITED
发明人： RINGE, Tushar P , JALAL, Jamshed , RAMAGIRI, Gurunath , TUMMALA, Ashok Kumar , WERKHEISER, Mark David
IPC分类号： G06F12/0806 , G06F12/0817 , G06F13/38 , G06F12/0813
摘要： An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

4. 发明申请

WO2020193949A1 SYSTEM, METHOD AND APPARATUS FOR ACCESSING SHARED MEMORY 审中-公开
公开(公告)号：WO2020193949A1
公开(公告)日：2020-10-01
申请号：PCT/GB2020/050686
申请日：2020-03-17
申请人： ARM LIMITED
发明人： RAMAGIRI, Gurunath , RINGE, Tushar P , PATEL, Mukesh , JALAL, Jamshed , TUMMALA, Ashok Kumar , WERKHEISER, Mark David
IPC分类号： G06F12/0831
摘要： A system,apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

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