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1. 发明申请

WO2007140424A3 CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW-LIKE SILICON DIOXIDE USING A SILICON CONTAINING PRECURSOR AND ATOMIC OXYGEN 审中-公开
标题翻译：使用含硅前体和原子氧的高品质流动二氧化硅的化学气相沉积
公开(公告)号：WO2007140424A3
公开(公告)日：2008-02-21
申请号：PCT/US2007069999
申请日：2007-05-30
申请人： APPLIED MATERIALS INC , INGLE NITIN K , YUAN ZHENG , GEE PAUL , SAPRE KEDAR
发明人： INGLE NITIN K , YUAN ZHENG , GEE PAUL , SAPRE KEDAR
IPC分类号： C23C16/40
CPC分类号： H01L21/3105 , C23C16/402 , C23C16/452 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02216 , H01L21/02274 , H01L21/02315 , H01L21/02337 , H01L21/31633
摘要： Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described.
摘要翻译：描述了在衬底上沉积氧化硅层的方法。该方法可以包括以下步骤：向沉积室提供衬底，在沉积室外产生原子氧前体，并将原子氧前体引入室中。所述方法还可以包括将硅前体引入沉积室，其中硅前体和原子氧前体首先在室中混合。硅前体和原子氧前体反应以在衬底上形成氧化硅层，并且沉积的氧化硅层可以退火。还描述了在衬底上沉积氧化硅层的系统。

2. 发明申请

WO2013049173A3 IMPROVED INTRENCH PROFILE 审中-公开
标题翻译：改进的英语资料
公开(公告)号：WO2013049173A3
公开(公告)日：2013-06-13
申请号：PCT/US2012057294
申请日：2012-09-26
申请人： APPLIED MATERIALS INC , SAPRE KEDAR , INGLE NITIN K , TANG JING
发明人： SAPRE KEDAR , INGLE NITIN K , TANG JING
IPC分类号： H01L21/762 , H01L21/205 , H01L21/31
CPC分类号： H01L21/3065 , H01L21/3081 , H01L21/76224
摘要： A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.
摘要翻译：描述了蚀刻半导体衬底中的凹陷的方法。该方法可以包括在衬底的具有第一密度的衬底的沟槽中形成电介质衬里层。该方法还可以包括至少部分地在衬垫层上的沟槽中沉积第二介电层。第二介电层在沉积之后最初可以是可流动的，并且具有小于衬里的第一密度的第二密度。该方法可进一步包括将衬底暴露于干蚀刻剂，其中蚀刻剂去除第一衬层和第二介电层的一部分以形成凹槽，其中干蚀刻剂包括含氟化合物和分子氢，并且其中用于去除第一电介质衬垫层以去除第二电介质层的蚀刻速率比为约1：1.2至约1：1。

3. 发明申请

WO2011112330A2 REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR 审中-公开
标题翻译：使用BIS（二乙基氨基）硅烷（C8H22N2Si）作为硅前体的减少图案加载
公开(公告)号：WO2011112330A2
公开(公告)日：2011-09-15
申请号：PCT/US2011025050
申请日：2011-02-16
申请人： APPLIED MATERIALS INC , KWESKIN SASHA , GEE PAUL EDWARD , VENKATARAMAN SHANKAR , SAPRE KEDAR
发明人： KWESKIN SASHA , GEE PAUL EDWARD , VENKATARAMAN SHANKAR , SAPRE KEDAR
IPC分类号： H01L21/205
CPC分类号： H01L21/02219 , C23C16/401 , H01L21/02164 , H01L21/02271
摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
摘要翻译：本公开的方面涉及在图案化衬底上沉积电介质层的方法。在实施方案中，通过将BIS（二氯乙烯）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得在图案化的衬底表面上实现相对均匀的电介质生长速率。根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

4. 发明申请

WO2011123217A3 SILICON-OZONE CVD WITH REDUCED PATTERN LOADING USING INCUBATION PERIOD DEPOSITION 审中-公开
标题翻译：使用沉积期沉积的减少图案加载的硅酮CVD
公开(公告)号：WO2011123217A3
公开(公告)日：2011-11-24
申请号：PCT/US2011027246
申请日：2011-03-04
申请人： APPLIED MATERIALS INC , KWESKIN SASHA , GEE PAUL EDWARD , VENKATARAMAN SHANKAR , SAPRE KEDAR
发明人： KWESKIN SASHA , GEE PAUL EDWARD , VENKATARAMAN SHANKAR , SAPRE KEDAR
IPC分类号： C23C16/40 , C23C16/04 , C23C16/50 , H01L21/205
CPC分类号： H01L21/02164 , C23C16/401 , C23C16/45523 , H01L21/0228
摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.
摘要翻译：本公开的方面涉及在图案化衬底上沉积保形氧化硅层的方法。在实施例中，通过将含硅前体和臭氧流入处理室来沉积电介质层，使得跨越具有异质材料的图案化衬底表面和/或异质图案密度分布实现相对均匀的介电生长速率。根据实施例生长的电介质层的沉积可以降低对下层材料和图案密度的依赖性，同时仍然适用于非牺牲应用。依靠图案密度的减少是通过在潜伏期结束时终止沉积来实现的。多个沉积循环可以串联进行，因为在沉积停顿之后潜伏期的有益特性可以重复。

5. 发明申请

WO2011129957A3 PREFERENTIAL DIELECTRIC GAPFILL 审中-公开
标题翻译：优选电介质
公开(公告)号：WO2011129957A3
公开(公告)日：2012-01-19
申请号：PCT/US2011029428
申请日：2011-03-22
申请人： APPLIED MATERIALS INC , KWESKIN SASHA , HAMANA HIROSHI , GEE PAUL EDWARD , VENKATARAMAN SHANKAR , SAPRE KEDAR
发明人： KWESKIN SASHA , HAMANA HIROSHI , GEE PAUL EDWARD , VENKATARAMAN SHANKAR , SAPRE KEDAR
IPC分类号： H01L21/316 , H01L21/31
CPC分类号： H01L21/76229 , H01L21/67017
摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.
摘要翻译：本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分。狭窄的沟槽用致密材料填充，而开放区域被一层致密材料和更多孔的材料覆盖。此时可以通过湿蚀刻在较宽的沟槽中去除介电材料，同时保留窄沟槽中的致密材料。

6. 发明申请

WO2011112402A2 IMPROVING CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS 审中-公开
标题翻译：改善深奥维思德侧壁氧化物层的一致性
公开(公告)号：WO2011112402A2
公开(公告)日：2011-09-15
申请号：PCT/US2011026834
申请日：2011-03-02
申请人： APPLIED MATERIALS INC , HUA ZHONG QIANG , HERNANDEZ MANUEL A , LUO LEI , SAPRE KEDAR
发明人： HUA ZHONG QIANG , HERNANDEZ MANUEL A , LUO LEI , SAPRE KEDAR
IPC分类号： H01L21/316
CPC分类号： H01L21/76898
摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 µm from a top surface of the nitride layer and an opening of less than about 10 µm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450°C, where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.
摘要翻译：一种用于改善沿着半导体衬底中的通孔的侧壁的氧化物层的共形性的方法包括在半导体衬底的上表面上方形成氮化物层并且形成延伸穿过氮化物层并进入半导体衬底的通孔。通孔可以具有距离氮化物层的顶表面至少约50μm的深度以及在氮化物层的顶表面处小于约10μm的开口。该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。可以使用热化学气相沉积（CVD）工艺在低于约450℃的温度下形成氧化物层，其中在通孔底部的氧化物层的厚度为至少约50％的厚度氧化层位于氮化层的顶部表面。

7. 发明申请

WO2011112518A2 METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS 审中-公开
标题翻译：形成低湿度电介质膜的方法
公开(公告)号：WO2011112518A2
公开(公告)日：2011-09-15
申请号：PCT/US2011027422
申请日：2011-03-07
申请人： APPLIED MATERIALS INC , HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , CAO ZHITAO , SAPRE KEDAR , BHATNAGAR AJAY
发明人： HUA ZHONG QIANG , LUO LEI , HERNANDEZ MANUEL A , CAO ZHITAO , SAPRE KEDAR , BHATNAGAR AJAY
IPC分类号： H01L21/205
CPC分类号： H01L21/02164 , C23C16/40 , C23C16/56 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02362
摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450°C or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450°C or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.
摘要翻译：用于在衬底上形成预金属电介质（PMD）层或金属间电介质（IMD）层的方法包括将衬底放置在化学气相沉积（CVD）处理室中，并在衬底上形成第一氧化物层 CVD处理室。第一氧化物层使用热CVD工艺在约450℃或更低的温度和低于大气压的压力下形成。该方法还包括在CVD工艺室中的第一氧化物层上形成第二氧化物层。使用等离子体增强化学气相沉积（PECVD）工艺在约450℃或更低的温度和低于大气压的压力下形成第二氧化物层。在形成第一氧化物层和第二氧化物层期间衬底保留在CVD处理室中。

8. 发明申请

WO2011025655A3 SILICON-SELECTIVE DRY ETCH FOR CARBON-CONTAINING FILMS 审中-公开
标题翻译：用于含碳膜的硅选择干燥剂
公开(公告)号：WO2011025655A3
公开(公告)日：2011-05-19
申请号：PCT/US2010045056
申请日：2010-08-10
申请人： APPLIED MATERIALS INC , SAPRE KEDAR , TANG JING , WANG LINLIN , MALLICK ABHIJIT BASU , INGLE NITIN
发明人： SAPRE KEDAR , TANG JING , WANG LINLIN , MALLICK ABHIJIT BASU , INGLE NITIN
IPC分类号： H01L21/3065 , B44C1/22 , G03F7/42
CPC分类号： H01L21/3065 , H01L21/31116
摘要： A method of etching silicon-and-carbon-containing material is described and includes a SiConiTM etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConiTM etch reducing the carbon content in the near surface region and allowing the SiConiTM etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConiTM etch further improving the effective etch rate.
摘要翻译：描述了一种蚀刻含硅和碳的材料的方法，并且包括结合活性氧流的SiConiTM蚀刻。可以在SiConiTM蚀刻之前引入活性氧，从而减少近表面区域中的碳含量，并允许SiConiTM蚀刻进行得更快。或者，可以在SiConiTM蚀刻期间引入活性氧，进一步提高有效蚀刻速率。

9. 发明申请

WO2013049223A3 INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION 审中-公开
标题翻译：用于半导体集成的敏感干燥除去过程
公开(公告)号：WO2013049223A3
公开(公告)日：2013-05-23
申请号：PCT/US2012057358
申请日：2012-09-26
申请人： APPLIED MATERIALS INC , SAPRE KEDAR , MININNI ROSSELLA , TANG JING
发明人： SAPRE KEDAR , MININNI ROSSELLA , TANG JING
IPC分类号： H01L21/311 , H01L21/31
CPC分类号： H01L29/401 , H01L21/31116 , H01L29/66545
摘要： Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF.
摘要翻译：公开了从半导体衬底的表面沉积和蚀刻电介质层的方法。所述方法可以包括在HF水溶液中沉积具有第一湿蚀刻速率的第一介电层。所述方法还可以包括沉积第二介电层，其可以在沉积之后最初可流动，并且第二介电层可以具有高于第一湿蚀刻速率的HF水溶液中的第二湿蚀刻速率。所述方法可以进一步包括用蚀刻剂气体混合物蚀刻第一和第二介电层，其中第一和第二介电层具有比第二湿蚀刻速率与第一湿蚀刻的比率更接近的蚀刻速率比在HF水溶液中。

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