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1. 发明申请

WO2005071738A3 SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE 审中-公开
标题翻译：浅沟槽隔离过程与结构
公开(公告)号：WO2005071738A3
公开(公告)日：2005-12-08
申请号：PCT/US2004043107
申请日：2004-12-21
申请人： ADVANCED MICRO DEVICES INC , XIANG QI , PAN JAMES N , GOO JUNG-SUK
发明人： XIANG QI , PAN JAMES N , GOO JUNG-SUK
IPC分类号： H01L21/336 , H01L21/762 , H01L29/10 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material (36) is formed after the trench (34) is formed. The process can be utilized on a compound semiconductor layer (15) above a buried oxide (Box) layer (14).
摘要翻译：制造集成电路（IC）的方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。应变材料（36）在沟槽（34）形成之后形成。该过程可以用在掩埋氧化物（Box）层（14）上方的化合物半导体层（15）上。

2. 发明申请

WO2005048320A2 METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FORM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 审中-公开
标题翻译：集成具有不同工作功能的金属以形成具有高K栅介电及相关结构的CMOS栅极的方法
公开(公告)号：WO2005048320A2
公开(公告)日：2005-05-26
申请号：PCT/US2004028486
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES INC , XIANG QI , ZHONG HUICAI , GOO JUNG-SUK , HOLBROOK ALLISON KAY , JEON JOONG S , KLUTH GEORGE JONATHAN
发明人： XIANG QI , ZHONG HUICAI , GOO JUNG-SUK , HOLBROOK ALLISON KAY , JEON JOONG S , KLUTH GEORGE JONATHAN
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/00
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).
摘要翻译：根据一个示例性实施例，用于将第一金属层（206）和第二金属层（208）集成在衬底（202）上以形成双金属NMOS栅极（226）和PMOS栅极（228）的方法包括沉积（150）在衬底（202）的NMOS区域（210）和PMOS区域（212）上形成层（204）。该方法还包括在介电层（204）上沉积（150）第一金属层（206）。该方法还包括在第一金属层（206）上沉积（150）第二金属层（208）。该方法进一步包括在衬底（202）的NMOS区域（210）中注入（152）氮并且将第一金属层（206）的第一部分转换（154）成金属氧化物层（220）并且将第二部分的第一金属层（206）进入金属氮化物层（218）。该方法还包括形成（156）NMOS栅极（226）和PMOS栅极（228），其中NMOS栅极（226）包括金属氮化物层（218）的片段（234），并且PMOS栅极（228）包括金属氧化物层（220）的区段（242）。

3. 发明申请

WO2005020323A3 FIELD EFFECT TRANSISTOR HAVING INCREASED CARRIER MOBILITY 审中-公开
标题翻译：场效应晶体管具有增加的载流子迁移率
公开(公告)号：WO2005020323A3
公开(公告)日：2005-05-06
申请号：PCT/US2004025565
申请日：2004-08-05
申请人： ADVANCED MICRO DEVICES INC , XIANG QI , ANG BOON YONG , GOO JUNG-SUK
发明人： XIANG QI , GOO JUNG-SUK
IPC分类号： H01L29/02 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/02 , H01L29/4925 , H01L29/513 , H01L29/78 , H01L29/7845 , Y10S438/938
摘要： According to one exemplary embodiment, a FET which is situated over a substrate (104), comprises a channel (112) situated in the substrate (104). The FET further comprises a first gate dielectric (116) situated over the channel (112), where the first gate dielectric (116) has a first coefficient of thermal expansion. The FET further comprises a first gate electrode (114) situated over the first gate dielectric (116), where the first gate electrode (114) has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel (112).
摘要翻译：根据一个示例性实施例，位于衬底（104）上的FET包括位于衬底（104）中的沟道（112）。 FET还包括位于沟道（112）上的第一栅极电介质（116），其中第一栅极电介质（116）具有第一热膨胀系数。 FET还包括位于第一栅极电介质（116）上方的第一栅极电极（114），其中第一栅极电极（114）具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一栅极电极热膨胀系数，从而导致FET中载流子迁移率的增加。例如，第二热膨胀系数可以大于第一热膨胀系数。载流子迁移率的增加可能由例如在通道（112）中产生的拉伸应变引起。

4. 发明申请

WO2004061920A2 METHOD OF FORMING A THICK STRAINED SILICON LAYER AND SEMICONDUCTOR STRUCTURES INCORPORATING A THICK STRAINED SILICON LAYER 审中-公开
标题翻译：形成厚度很小的硅层的方法和掺入厚度有限的硅层的半导体结构
公开(公告)号：WO2004061920A2
公开(公告)日：2004-07-22
申请号：PCT/US0334673
申请日：2003-10-30
申请人： ADVANCED MICRO DEVICES INC
发明人： WANG HAIHONG , BESSER PAUL R , GOO JUNG-SUK , NGO MINH VAN , PATON ERIC N , XIANG QI
IPC分类号： H01L21/20 , H01L21/336 , H01L21/762 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76224 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A strained silicon layer (50) s grown on a layer of silicon germanium (40) and a layer of silicon germanium (52) is grown on the strained silicon (50) in a single continuous in situ deposition process with the strained silicon (50). Shallow trench isolations (48) are formed in the lower layer of silicon germanium (40) prior to formation of the strained silicon layer (50). The two silicon germanium layers (40, 52) effectively provide dual substrates at both surfaces of the strained silicon layer (50) that serve to maintain the tensile strain of the strained silicon layer (50) and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon (50) that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers (40, 52). The formation of shallow trench isolations (48) prior to formation of the strained silicon layer (50) avoids subjecting the strained silicon (50) layer to extreme thermal stresses and further reduces the formation of misfit dislocations.
摘要翻译：生长在硅锗层（40）和硅锗层（52）上的应变硅层（50）生长在应变硅（50）上，在单一的连续原位沉积工艺中与应变硅（50 ）。在形成应变硅层（50）之前，在硅锗的下层（40）中形成浅沟槽隔离（48）。两个硅锗层（40,42）有效地在应变硅层（50）的两个表面处有效地提供双重衬底，其用于保持应变硅层（50）的拉伸应变并且抵抗形成不合适的位错由加工过程中的温度变化引起。因此，对于硅锗层（40,52）的给定锗含量，可以在后续处理期间生长而不显着失配位错的应变硅（50）的临界厚度被有效地加倍。在形成应变硅层（50）之前形成浅沟槽隔离（48）避免使应变硅（50）层受到极端的热应力，并进一步减少失配位错的形成。

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