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1. 发明申请

WO2005053035A1 LOW-POWER MULTIPLE-CHANNEL FULLY DEPLETED QUANTUM WELL CMOSFETS 审中-公开
标题翻译：低功耗多通道全通道量子阱CMOSFETs
公开(公告)号：WO2005053035A1
公开(公告)日：2005-06-09
申请号：PCT/US2004/033413
申请日：2004-10-08
申请人： ADVANCED MICRO DEVICES, INC. , PAN, James, N. , PELLERIN, John, G. , CHEEK, Jon, D.
发明人： PAN, James, N. , PELLERIN, John, G. , CHEEK, Jon, D.
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions (15) are provided on a substrate (12) with a gate electrode (16) formed on the uppermost channel region (15), separated by a gate oxide (14c), for example. The vertical stacking of multiple channels (15) and the gate electrode (16) permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域（15）设置在基板（12）上，其栅极电极（16）形成在最上通道区域（15）上，例如由栅极氧化物（14c）分开。多个通道（15）和栅电极（16）的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

2. 发明申请

WO2005093825A1 METHOD OF REDUCING STI DIVOT FORMATION DURING SEMICONDUCTOR DEVICE FABRICATION 审中-公开
标题翻译：在半导体器件制造过程中减少STI DIVOT形成的方法
公开(公告)号：WO2005093825A1
公开(公告)日：2005-10-06
申请号：PCT/US2005/006177
申请日：2005-02-26
申请人： ADVANCED MICRO DEVICES, INC. , BONSER, Douglas, J. , GROSCHOPF, Johannes , DAKSHINA-MURTHY, Srikanteswara , PELLERIN, John, G. , CHEEK, Jon, D.
发明人： BONSER, Douglas, J. , GROSCHOPF, Johannes , DAKSHINA-MURTHY, Srikanteswara , PELLERIN, John, G. , CHEEK, Jon, D.
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer (52), e.g., no thicker than 400Å. The very thin nitride polish stop layer (52) is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions (80), and is removed prior to gate oxide (101) and gate electrode (100) formation.
摘要翻译：通过使用非常薄的氮化物抛光停止层（52）（例如不大于400）来消除或基本上减少STI形成。在随后的掩模，植入和清洁步骤中，非常薄的氮化物抛光停止层（52）被保持就位以形成掺杂剂区域（80），并且在形成栅极氧化物（101）和栅电极（100）之前被去除。

3. 发明申请

WO2009114187A1 INTEGRATED CIRCUIT HAVING LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE 审中-公开
标题翻译：具有长和短通道金属门装置的集成电路及其制造方法
公开(公告)号：WO2009114187A1
公开(公告)日：2009-09-17
申请号：PCT/US2009/001617
申请日：2009-03-13
申请人： ADVANCED MICRO DEVICES, INC. , CARTER, Richard, J. , HARGROVE, Michael, J. , KLUTH, George, J. , PELLERIN, John, G.
发明人： CARTER, Richard, J. , HARGROVE, Michael, J. , KLUTH, George, J. , PELLERIN, John, G.
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device (16) and a long channel (LC) device (18) each overlaid by an interlayer dielectric (75). The SC device (16) has an SC gate stack (34), and the LC device (18) initially has a dummy gate (50). In one embodiment, the method includes the steps of removing the dummy gate (50) to form an LC device trench (96) and depositing metal gate material (98) over the SC device (16) and the LC device (18). The metal gate material (98) contacts the SC gate stack (34) and substantially fills the LC device trench (96).
摘要翻译：提供了一种用于制造集成电路的方法，该集成电路包括每个由层间电介质（75）覆盖的短沟道（SC）器件（16）和长沟道（LC）器件（18）。 SC设备（16）具有SC门堆叠（34），并且LC设备（18）最初具有虚拟门（50）。在一个实施例中，该方法包括以下步骤：去除伪栅极（50）以形成LC器件沟槽（96）并在SC器件（16）和LC器件（18）上沉积金属栅极材料（98）。金属栅极材料（98）接触SC栅极堆叠（34）并且基本上填充LC器件沟槽（96）。

4. 发明申请

WO2002071476A3 METHOD OF FORMING CONDUCTIVE INTERCONNECTIONS IN POROUS INSULATING FILMS AND ASSOCIATED DEVICE 审中-公开
公开(公告)号：WO2002071476A3
公开(公告)日：2002-09-12
申请号：PCT/US2002/003945
申请日：2002-02-01
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PELLERIN, John, G. , WRISTERS, Derick, J.
IPC分类号： H01L21/768
摘要： The integrated circuit device disclosed herein comprises an insulating layer (32) comprised of a first insulating material that has an opening (36) formed therein as defined by at least one sidewall (36A), at least one sidewall spacer (40) positioned adjacent the sidewall (36A) of the opening (36), the sidewall spacer (40) being comprised of a second insulating material, and a conductive interconnection (42) formed in the opening (36) in the insulating layer (32). In a further embodiment, the first insulating material has a dielectric constant less than approximately 3, and a density less than approximately 1.2 grams/cc, whereas the second insulating material has a dielectric constant less than approximately 7 and a density less than approximately 3 grams/cc. The method disclosed herein comprises forming an opening (36) in a first layer (32) of a first insulating material, the opening (36) being defined by at least one sidewall (36A), and conformally depositing a second layer (38) comprised of a second insulating material in the opening (36) above the sidewall (36A). The method further comprises performing an anisotropic etching process on the second layer to define a sidewall spacer (40) comprised of the second insulating material positioned adjacent the sidewall (36A) of the opening (36), and forming a conductive interconnection (42) in the opening (36) in the insulating layer (32) between the sidewall spacer (40).

5. 发明申请

WO2003054948A1 NITRIDE OFFSET SPACER TO MINIMIZE SILICON RECESS BY USING POLY REOXIDATION LAYER AS ETCH STOP LAYER 审中-公开
标题翻译： NITRIDE偏移间隔器，通过使用多重再氧化层作为止蚀层来最小化硅的回收
公开(公告)号：WO2003054948A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/041105
申请日：2002-12-19
申请人： ADVANCED MICRO DEVICES, INC.
发明人： QI, Wen-Jie , PELLERIN, John, G. , EN, William, G. , MICHAEL, Mark, W. , CHAN, Darin, A.
IPC分类号： H01L21/31
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L21/3185 , H01L29/6656
摘要： A method of forming a semiconductor device provides a gate electrode (22) on a substrate (20) and forms a polysilicon reoxidation layer (26) over the substrate (20) and the gate electrode (22). A nitride layer (28) is deposited over the polysilicon reoxydation layer (26) and anisotropically etched. The etching stops on the polysilicon reoxidation layer (26), with nitride offset spacers (30) being formed on the gate electrode (22). The use of the polysilicon reoxidation layer (26) as an etch stop layer prevents the gouging of the silicon substrate (20) underneath the nitride layer (28), while allowing the offset spacers (30) to be formed.
摘要翻译：形成半导体器件的方法在衬底（20）上提供栅电极（22）并在衬底（20）和栅电极（22）上形成多晶硅再氧化层（26）。氮化物层（28）沉积在多晶硅再氧化层（26）上并各向异性蚀刻。在多晶硅再氧化层（26）上停止蚀刻，在栅电极（22）上形成氮化物偏移间隔物（30）。多晶硅再氧化层（26）作为蚀刻停止层的使用防止了氮化物层（28）下面的硅衬底（20）的刨削，同时允许形成偏移间隔物（30）。

6. 发明申请

WO2002075781A2 METHOD OF FORMING SILICIDE CONTACTS AND DEVICE INCORPORATING SAME 审中-公开
标题翻译：形成硅氧烷接触的方法和包含它们的装置
公开(公告)号：WO2002075781A2
公开(公告)日：2002-09-26
申请号：PCT/US2002/002774
申请日：2002-02-01
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PELLERIN, John, G. , CHEEK, Jon, D. , DAWSON, Robert , HAUSE, Frederick, N. , LUNING, Scott, D.
IPC分类号： H01L
CPC分类号： H01L29/66507 , H01L21/823443 , H01L29/665 , H01L29/6653
摘要： A transistor, comprising a semiconducting substrate (30), a gate insulation layer (48) positioned above the substrate (30), agate electrode (46) positioned above the gate insulation layer (48), a plurality of source/drain regions formed in the substrate (30), a first (40A) and a second (52) sidewall spacer positioned adjacent the gate electrode (46), and a metal silicide layer (54) formed above each of the source/drain regions, a portion of the metal silicide layer (54) being positioned adjacent the first sidewall spacer (40A) and under the second sidewall spacer (52). The method comprises forming a transistor by forming a gate insulation layer (48) and a gate electrode (46) above a semiconducting substrate (30), forming a first sidewall spacer (40A) adjacent the gate electrode (46), forming a metal silicide layer (50) adjacent the first sidewall spacer (40A) and above previously formed implant regions in the substrate, forming a second sidewall spacer (52) above a portion of the metal silicide layer (50) and adjacent the first sidewall spacer (40A), and forming additional metal silicide material (50A) above the metal silicide layer (50) extending beyond the second sidewall spacer (52).
摘要翻译：一种晶体管，包括半导体衬底（30），位于衬底（30）上方的栅极绝缘层（48），位于栅极绝缘层（48）上方的玛瑙电极（46），多个源极/漏极区域基板（30），邻近栅电极（46）定位的第一（40A）和第二（52）侧壁间隔物，以及形成在每个源极/漏极区域上方的金属硅化物层（54）金属硅化物层（54）定位成邻近第一侧壁间隔物（40A）并位于第二侧壁间隔物（52）下方。该方法包括通过在半导体衬底（30）上形成栅极绝缘层（48）和栅电极（46）来形成晶体管，形成邻近栅电极（46）的第一侧壁间隔物（40A），形成金属硅化物邻近第一侧壁间隔物（40A）的层（50）以及衬底中先前形成的注入区域，在金属硅化物层（50）的一部分上方并邻近第一侧壁间隔物（40A）形成第二侧壁间隔物（52）并且在金属硅化物层（50）之上形成延伸超过第二侧壁间隔物（52）的附加金属硅化物材料（50A）。

7. 发明申请

WO2003054966A1 SOI DEVICE WITH DIFFERENT SILICON THICKNESSES 审中-公开
标题翻译：具有不同硅厚度的SOI器件
公开(公告)号：WO2003054966A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/041102
申请日：2002-12-19
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAN, Darin, A. , EN, William, G. , PELLERIN, John, G. , MICHAEL, Mark, W.
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer (14) over an insulating layer (12), and partially removing a first portion of the silicon layer (14). The silicon layer (14) includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer (14) initially can have the same thickness. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在绝缘层（12）上设置硅半导体层（14），并部分去除硅层（14）的第一部分。硅层（14）包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，硅层（14）的第一和第二部分最初可以具有相同的厚度。还公开了一种半导体器件。

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