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1. 发明申请

WO2012083012A1 DEVICE DISCOVERY AND TOPOLOGY REPORTING IN A COMBINED CPU/GPU ARCHITECTURE SYSTEM 审中-公开
标题翻译：组合CPU / GPU架构系统中的设备发现和拓扑报告
公开(公告)号：WO2012083012A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/065136
申请日：2011-12-15
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOGIES ULC , BLINZER, Paul , VAN DOORN, Leendert , CHENG, Jeffrey , TERRY, Elene , WOLLER, Thomas , RAHMAN, Arshad
发明人： BLINZER, Paul , VAN DOORN, Leendert , CHENG, Jeffrey , TERRY, Elene , WOLLER, Thomas , RAHMAN, Arshad
IPC分类号： G06F9/46
CPC分类号： E21B4/14
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/ APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/ APD architecture system. The combined CPU/ APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/ APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：提供了作为组合的CPU / APD架构系统的一个方面的方法和装置，用于发现和报告与有效地调度和分发计算任务到组合的CPU / APD架构的各种计算资源相关的设备和系统拓扑的属性系统。组合的CPU / APD架构将CPU和APD统一在灵活的计算环境中。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构创建了可以构建现有和新的编程框架，语言和工具的基础。

2. 发明申请

WO2012082424A1 GRAPHICS PROCESSING DISPATCH FROM USER MODE 审中-公开
标题翻译：图形处理从用户模式进行分配
公开(公告)号：WO2012082424A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/063240
申请日：2011-12-05
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC , MCCRARY, Rex , HOUSTON, Michael , ROGERS, Philip, J. , CHENG, Jeffrey, G. , HUMMEL, Mark , BLINZER, Paul
发明人： MCCRARY, Rex , HOUSTON, Michael , ROGERS, Philip, J. , CHENG, Jeffrey, G. , HUMMEL, Mark , BLINZER, Paul
IPC分类号： G06F9/48
CPC分类号： G06F9/545 , G06F9/544
摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

3. 发明申请

WO2012082423A1 GRAPHICS COMPUTE PROCESS SCHEDULING 审中-公开
标题翻译：图形计算过程调度
公开(公告)号：WO2012082423A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/063238
申请日：2011-12-05
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC , CHENG, Jeffrey, G. , HUMMEL, Mark , VANDOORN, Leendert , BLINZER, Paul
发明人： CHENG, Jeffrey, G. , HUMMEL, Mark , VANDOORN, Leendert , BLINZER, Paul
IPC分类号： G06F9/48
CPC分类号： G06F9/545 , G06F2209/509
摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

4. 发明申请

WO2012082421A1 ACCESSIBILITY OF GRAPHICS PROCESSING COMPUTE RESOURCES 审中-公开
标题翻译：图形处理计算资源的可访问性
公开(公告)号：WO2012082421A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/063235
申请日：2011-12-05
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC , MCCRARY, Rex , HOUSTON, Michael , ROGERS, Philip, J. , CHENG, Jeffrey, G. , HUMMEL, Mark , MOORE, Chuck , VANDOORN, Leendert , BLINZER, Paul
发明人： MCCRARY, Rex , HOUSTON, Michael , ROGERS, Philip, J. , CHENG, Jeffrey, G. , HUMMEL, Mark , MOORE, Chuck , VANDOORN, Leendert , BLINZER, Paul
IPC分类号： G06F9/48
CPC分类号： G06F9/5044 , G06F2209/509
摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

5. 发明申请

WO2009076671A2 DRIVER ARCHITECTURE FOR COMPUTING DEVICE HAVING MULTIPLE GRAPHICS SUBSYSTEMS, REDUCED POWER CONSUMPTION MODES, SOFTWARE AND METHODS 审中-公开
标题翻译：具有多个图形子系统的计算设备的驱动器架构，降低功耗模式，软件和方法
公开(公告)号：WO2009076671A2
公开(公告)日：2009-06-18
申请号：PCT/US2008/086835
申请日：2008-12-15
申请人： ADVANCED MICRO DEVICES, INC. , MUMMAH, Phil , BLINZER, Paul
发明人： BLINZER, Paul
IPC分类号： G06F3/038 , G06F15/16
CPC分类号： G06F1/3203 , G06F1/3265 , G06F1/3293 , G09G5/12 , G09G5/363 , G09G2330/022 , G09G2340/0435 , G09G2360/06 , G09G2370/04 , Y02D10/122 , Y02D10/153
摘要： Many computing devices may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities and may, for example, consume differing amounts of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems. A further proxy driver component routes calls (e.g. API/DDI calls) to one of said first and second driver components, in dependence on which of the first and second graphics system is in use.
摘要翻译：许多计算设备现在可以包括两个或更多个图形子系统。多个图形子系统可以具有不同的能力，并且可以例如消耗不同量的电功率，一个子系统比其他子系统消耗更多的平均功率。较高功率消耗的图形子系统可以耦合到该设备，并且被代替或者除了低功耗的图形子系统之外使用，导致更高的性能或附加能力，但增加了整体功耗。通过从使用较高功耗的图形子系统转换到较低功耗的图形子系统，在将较高功率消耗的图形子系统置于较低功耗模式的同时，总体功耗降低。处理器执行应用软件和驱动程序软件。驱动器软件包括用于分别控制第一和第二图形子系统的操作的第一和第二驱动器组件。根据第一和第二图形系统中的哪一个在使用中，另外的代理驱动器组件将呼叫（例如，API / DDI呼叫）路由到所述第一和第二驱动器组件之一。

6. 发明申请

WO2023091459A1 HIERARCHICAL ASYMMETRIC CORE ATTRIBUTE DETECTION 审中-公开
公开(公告)号：WO2023091459A1
公开(公告)日：2023-05-25
申请号：PCT/US2022/050061
申请日：2022-11-16
申请人： ADVANCED MICRO DEVICES, INC.
发明人： GOLDEN, Michael , BLINZER, Paul , TALISAYON, Magiting , MASANAM, Srikanth , BUTANI, Ripal , SWAMINATHAN, Upasanah
IPC分类号： G06F9/50 , G06F9/38
摘要： Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.

7. 发明申请

WO2020243043A1 PROVIDING COPIES OF INPUT-OUTPUT MEMORY MANAGEMENT UNIT REGISTERS TO GUEST OPERATING SYSTEMS 审中-公开
公开(公告)号：WO2020243043A1
公开(公告)日：2020-12-03
申请号：PCT/US2020/034455
申请日：2020-05-25
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAN, Maggie , NG, Phillip , BLINZER, Paul
IPC分类号： G06F11/14 , G06F9/455
摘要： An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

8. 发明申请

WO2021055908A1 PROVIDING INTERRUPTS FROM AN INPUT-OUTPUT MEMORY MANAGEMENT UNIT TO GUEST OPERATING SYSTEMS 审中-公开
公开(公告)号：WO2021055908A1
公开(公告)日：2021-03-25
申请号：PCT/US2020/051706
申请日：2020-09-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAN, Maggie , NG, Phillip , BLINZER, Paul
IPC分类号： G06F9/455 , G06F9/48 , G06F12/109 , G06F12/1009 , G06F12/1081
摘要： An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

9. 发明申请

WO2021035134A1 A NETWORKED INPUT/OUTPUT MEMORY MANAGEMENT UNIT 审中-公开
公开(公告)号：WO2021035134A1
公开(公告)日：2021-02-25
申请号：PCT/US2020/047376
申请日：2020-08-21
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： ARORA, Sonu , BLINZER, Paul , NG, Philip , RAVAL, Nippon Harshadk
IPC分类号： G06F12/109 , G06F12/1027 , G06F12/1009 , G06T1/60
摘要： A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

10. 发明申请

WO2013090594A2 INFRASTRUCTURE SUPPORT FOR GPU MEMORY PAGING WITHOUT OPERATING SYSTEM INTEGRATION 审中-公开
标题翻译：基于GPU的内存支持基础架构支持，无需运行系统集成
公开(公告)号：WO2013090594A2
公开(公告)日：2013-06-20
申请号：PCT/US2012/069531
申请日：2012-12-13
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WOLLER, Thomas, Roy , VAN DOORN, Leendert, Peter , RAHMAN, Arshad , BLINZER, Paul , CHENG, Gongxian, Jeffrey , TERRY, Elene
IPC分类号： G06F9/38
CPC分类号： G06F12/1009 , G06F9/3004 , G06F9/3881 , G06F12/1081 , G06F2009/3883 , G06F2212/683
摘要： In a CPU of the combined CPU/GPU architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to a GPU, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 Page Table invalidations.
摘要翻译：在组合的CPU / GPU架构系统的CPU中，CPU具有多个CPU核心，每个核心具有用于接收物理页面/页面目录基址的第一机器特定寄存器，用于接收物理地址指向到由通信地耦合到GPU的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制已经更新了CPU核心的寄存器，并且响应于控制寄存器已被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中，物理地址能够接收影响IOMMUv2 Page表无效的写入。

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