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1. 发明申请

WO2021055908A1 PROVIDING INTERRUPTS FROM AN INPUT-OUTPUT MEMORY MANAGEMENT UNIT TO GUEST OPERATING SYSTEMS 审中-公开
公开(公告)号：WO2021055908A1
公开(公告)日：2021-03-25
申请号：PCT/US2020/051706
申请日：2020-09-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAN, Maggie , NG, Phillip , BLINZER, Paul
IPC分类号： G06F9/455 , G06F9/48 , G06F12/109 , G06F12/1009 , G06F12/1081
摘要： An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

2. 发明申请

WO2020251790A1 GUEST OPERATING SYSTEM BUFFER AND LOG ACCESS BY AN INPUT-OUTPUT MEMORY MANAGEMENT UNIT 审中-公开
公开(公告)号：WO2020251790A1
公开(公告)日：2020-12-17
申请号：PCT/US2020/035506
申请日：2020-06-01
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAN, Maggie , NG, Phillip , BLINZER, Paul
IPC分类号： G06F9/455
摘要： An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.

3. 发明申请

WO2020243043A1 PROVIDING COPIES OF INPUT-OUTPUT MEMORY MANAGEMENT UNIT REGISTERS TO GUEST OPERATING SYSTEMS 审中-公开
公开(公告)号：WO2020243043A1
公开(公告)日：2020-12-03
申请号：PCT/US2020/034455
申请日：2020-05-25
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAN, Maggie , NG, Phillip , BLINZER, Paul
IPC分类号： G06F11/14 , G06F9/455
摘要： An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

4. 发明申请

WO2018075535A1 DIRECT MEMORY ACCESS AUTHORIZATION IN A PROCESSING SYSTEM 审中-公开
标题翻译：处理系统中的直接存储器访问授权
公开(公告)号：WO2018075535A1
公开(公告)日：2018-04-26
申请号：PCT/US2017/057005
申请日：2017-10-17
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： KAPLAN, David , CHAN, Maggie , NG, Philip
IPC分类号： G06F21/62 , G06F21/60 , G06F9/455
摘要： A processor [102] employs a hardware encryption module [120] in the memory access path between an input/out device [106] and memory [104] to cryptographically isolate secure information. In some embodiments, the encryption module is located at a memory controller [116] of the processor, and each memory access request provided to the memory controller includes VM tag value identifying the source of the memory access request. The VM tag is determined based on a requestor id identifying the source of the memory access request. The encryption module performs encryption (for write accesses) or decryption (for read accesses) of the data associated with the memory access based on an encryption key associated with the VM tag.
摘要翻译：处理器[102]在输入/输出设备[106]和存储器[104]之间的存储器访问路径中采用硬件加密模块[120]来加密隔离安全信息。在一些实施例中，加密模块位于处理器的存储器控制器[116]处，并且提供给存储器控制器的每个存储器访问请求包括标识存储器访问请求的源的VM标签值。 VM标签基于标识存储器访问请求的来源的请求者ID来确定。加密模块基于与VM标签相关联的加密密钥执行与存储器访问相关联的数据的加密（用于写入访问）或解密（用于读取访问）。

5. 发明申请

WO2015061731A1 INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE 审中-公开
标题翻译：输入/输出存储器映射单元和北桥
公开(公告)号：WO2015061731A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/062249
申请日：2014-10-24
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： KALYANASUNDHARAM, Vydhyanathan , NG, Philip , CHAN, Maggie , CUEVA, Vincent , CHEN, Liang , ASARO, Anthony , MIRZA, Jimshed , DONLEY, Greggory Douglas , BROUSSARD, Bryan , TSIEN, Benjamin , ADIRI, Yaniv
IPC分类号： G06F12/02 , G06F12/06 , G11C7/10
CPC分类号： G06F12/1009 , G06F12/1045 , G06F12/12 , G06F2212/684
摘要： The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/ probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.
摘要翻译：本发明通过新的原子测试[0]和OR和Mask来提供在硬件中的页表访问和脏位管理。本发明还提供了一种使ACE能够进行CCI翻译的垫圈。该垫片进一步提供了ACE和CCI之间的请求转换，针对受害者和探针冲突的死锁避免，ARM屏障处理和电源管理交互。本发明还提供了一种用于ARM受害者/探测器碰撞处理的解决方案，其使统一的北桥陷入僵局。这些解决方案包括一个专用的回写虚拟通道，使用4跳协议的IO请求的探测器和MCT中的WrBack重新排序能力，其中受害者通过数据通过请求时更新旧的请求。

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