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1. 发明申请

WO2021126837A1 AUTOMATIC VOLTAGE RECONFIGURATION 审中-公开
公开(公告)号：WO2021126837A1
公开(公告)日：2021-06-24
申请号：PCT/US2020/065099
申请日：2020-12-15
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： AHRENS, Jerry A. , MEHRA, Amitabh , HARWANI, Anil , ALVERSON, William R. , LEY, Grant E. , LEE, Charles Sy
IPC分类号： G06F1/3296 , G06F11/24 , G01R31/3004 , G06F1/3234
摘要： Automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads; determining, based on the user-specified workloads, a respective minimum safe voltage for each core of one or more cores; and modifying a respective voltage configuration for each core of the one or more cores based on the respective minimum safe voltage.

2. 发明申请

WO2022271563A1 SYSTEM AND METHOD FOR CONTROLLING ELECTRICAL CURRENT SUPPLY IN A MULTI-PROCESSOR CORE SYSTEM VIA INSTRUCTION PER CYCLE REDUCTION 审中-公开
公开(公告)号：WO2022271563A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/034052
申请日：2022-06-17
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MEHRA, Amitabh , BORN, Richard Martin , SRINIVASAN, Sriram , KOMATIREDDY, Sneha , GOLDEN, Michael L. , MAN, Xiuting Kaleen C. , DEVI, Gokul Subramani Ramalingam Lakshmi , HE, Xiaojie
IPC分类号： G06F1/3206 , G06F1/324 , G06F1/3234 , G06F1/3296 , G06F1/28 , G06F1/10 , G06F1/3243
摘要： Methods and apparatuses control electrical current supplied to a plurality of processing units (102) in a multi-processor system. A plurality of current usage information (108) corresponding to the processing units are received by a controller (104) to determine a threshold current for each of the processing units. The controller determines a frequency reduction action (116) and an instructions-per-cycle (IPC) reduction action (202) for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.

3. 发明申请

WO2021118753A1 METHOD AND APPARATUS FOR MANAGING PROCESSOR FUNCTIONALITY 审中-公开
公开(公告)号：WO2021118753A1
公开(公告)日：2021-06-17
申请号：PCT/US2020/060295
申请日：2020-11-12
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： MEHRA, Amitabh , HARWANI, Anil , ALVERSON, William Robert , AHRENS, Jerry Anton , LEE, Charles Sum Yuen , ABSHIER, John William
IPC分类号： G06F9/48 , G06F11/30 , G06F1/324
摘要： A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.

4. 发明申请

WO2018013155A1 MANAGING FREQUENCY CHANGES OF CLOCK SIGNALS ACROSS DIFFERENT CLOCK DOMAINS 审中-公开
标题翻译：管理不同时钟域的时钟信号频率变化
公开(公告)号：WO2018013155A1
公开(公告)日：2018-01-18
申请号：PCT/US2016/051813
申请日：2016-09-15
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KOMMRUSCH, Steven , MEHRA, Amitabh , BORN, Richard Martin
IPC分类号： G06F1/08 , G06F1/10
摘要： A processor (100) maintains a minimum setup time for data being transferred between clock domains (102, 103), including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules (122, 124) that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.
摘要翻译：处理器（100）维持用于在时钟域（102,103）之间传送的数据的最小建立时间，包括响应于时钟信号中的频率变化维持最小建立时间至少其中一个时钟域。处理器采用监视每个时钟域中的时钟边沿的一个或多个控制模块（122,124），以确保数据不被接收时钟域从存储位置访问，直到在传送中经过最小数量的阶段数据写入存储位置之后的时钟域。此外，响应于一个或两个时钟域处的时钟频率的变化，控制模块维持最小建立时间。

5. 发明申请

WO2023278193A1 SYSTEM AND METHOD FOR ENABLING CLOCK STRETCHING DURING OVERCLOCKING IN RESPONSE TO VOLTAGE DROOP 审中-公开
公开(公告)号：WO2023278193A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/034192
申请日：2022-06-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MEHRA, Amitabh , AHRENS, Jerry A. , HARWANI, Anil , BORN, Richard Martin , ROBINSON, Dirk J. , ALVERSON, William R. , KNIGHT, Joshua Taylor
IPC分类号： G06F1/08 , G06F1/28 , H03K5/00006
摘要： Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

6. 发明申请

WO2019168944A1 ONBOARD MONITORING OF VOLTAGE LEVELS AND DROOP EVENTS 审中-公开
公开(公告)号：WO2019168944A1
公开(公告)日：2019-09-06
申请号：PCT/US2019/019783
申请日：2019-02-27
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MEHRA, Amitabh , LEWIS, Dana G.
IPC分类号： G06F1/32 , G01R19/255 , G01R19/00
摘要： A processor [100] includes a plurality of voltage droop detectors [130] positioned at multiple points of the processor. The detectors monitor voltage levels and alerts the processor if a droop event has been detected in real time. Multiple droops can be detected simultaneously, with each detected droop event generating an alert that is sent to a processor module, such as a clock control module, to act based on the detected droop. Each detector employs a ring oscillator [206] that generates a periodic signal and a corresponding count based on that signal, where the frequency of the signal varies based on a voltage at the corresponding point being monitored.

7. 发明申请

WO2019125569A1 PSEUDO-RANDOM LOGICAL TO PHYSICAL CORE ASSIGNMENT AT BOOT FOR AGE AVERAGING 审中-公开
公开(公告)号：WO2019125569A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/052456
申请日：2018-09-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MEHRA, Amitabh , BERNUCHO, Krishna Sai
IPC分类号： G06F9/50
CPC分类号： G06F9/4408 , G06F9/4403
摘要： A computing device (100) includes a processor (100) having a plurality of cores (111-114), a core translation component (616), and a core assignment component (617). The core translation component provides a set of registers (405), one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

8. 发明申请

WO2018013156A1 CLOCK ADJUSTMENT FOR VOLTAGE DROOP 审中-公开
标题翻译：时钟调整电压跌落
公开(公告)号：WO2018013156A1
公开(公告)日：2018-01-18
申请号：PCT/US2016/051814
申请日：2016-09-15
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KOMMRUSCH, Steven , MEHRA, Amitabh , BORN, Richard Martin , YOUNG, Bobby D.
IPC分类号： G06F11/07 , G06F11/30
摘要： A processor (100) adjusts frequencies of one or more clock signals (230) in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals (220, 221, 222, 223, 224, 225, 226, 227), each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.
摘要翻译：处理器（100）响应于处理器处的电压下垂来调整一个或多个时钟信号（230）的频率。处理器通过产生多个基本时钟信号（220,221,222,223,224,225,226,227）来产生至少一个时钟信号，每个基本时钟信号具有共同的频率但是不同的相位。处理器还产生多个使能信号，其中每个使能信号控制是否使用对应的一个基本时钟信号来产生时钟信号。使能信号因此确定时钟信号的频率。响应于检测到电压下降，处理器调整用于产生时钟信号的使能信号，从而降低时钟信号下垂的频率。

9. 发明申请

WO2021133506A1 METHOD AND APPARATUS FOR MANAGING OVERCLOCKING IN A DATA CENTER 审中-公开
公开(公告)号：WO2021133506A1
公开(公告)日：2021-07-01
申请号：PCT/US2020/062139
申请日：2020-11-25
申请人： ADVANCED MICRO DEVICES, INC.
发明人： MEHRA, Amitabh , BURLEY, Jeffrey N. , HARWANI, Anil
IPC分类号： G06F1/08 , G06F1/324 , H03L7/183 , G06F1/26 , G06F11/3055 , G06F11/3058
摘要： A method and apparatus for managing overclocking in a data center includes determining a frequency limit of a first processor of a first server in the data center. The voltage of the first processor is lowered to a stability point, and the frequency is lowered. The first server is tested for stability. Based upon the results of the test, the voltage and frequency modifications are deployed to a second processor of a second server in the data center.

10. 发明申请

WO2021127369A1 AUTOMATIC CENTRAL PROCESSING UNIT USAGE OPTIMIZATION 审中-公开
公开(公告)号：WO2021127369A1
公开(公告)日：2021-06-24
申请号：PCT/US2020/065905
申请日：2020-12-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： HARWANI, Anil , MEHRA, Amitabh , ALVERSON, William, R. , LEY, Grant, E. , AHRENS, Jerry, A. , MITCHELL, Kenneth
IPC分类号： G06F9/50 , G06F11/3024 , G06F11/3433 , G06F2209/501 , G06F2209/5018 , G06F2209/502 , G06F2209/508 , G06F9/48 , G06F9/5027 , G06F9/5066 , G06F9/5083 , G06F9/5094
摘要： Automatic central processing unit (CPU) usage optimization includes: monitoring performance activity of a workload comprising a plurality of threads; and modifying a resource allocation of a plurality of cores for the plurality of threads based on the performance activity.

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