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1. 发明申请

WO2004075221A2 MICRO FUSE 审中-公开
公开(公告)号：WO2004075221A2
公开(公告)日：2004-09-02
申请号：PCT/GB2004/000655
申请日：2004-02-18
申请人： CAVENDISH KINETICS LIMITED , VAN KAMPEN, Robert , SMITH, Charles, Gordon , KAZINSKI, Robert
发明人： VAN KAMPEN, Robert , SMITH, Charles, Gordon , KAZINSKI, Robert
IPC分类号： H01H
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A micro fuse for use in a semiconductor device. The micro fuse comprises an insulating substrate and an elongate metal fuse member, the fuse member being supported at either end on the substrate and including at least one fuse region suspended out of contact with the substrate and shaped such that, in use, a predetermined current can be applied to it to make it non-conducting. At least one barrier may be formed between the fuse region of the fuse member and the insulator. The fuse member may be formed from a readily oxidisable metal, such as Titanium, Tungsten, Tantalum, Copper or Aluminium. The fuse member may have two or more fuse regions, with a region between adjacent fuse regions being supported by a metal track. In this case, the fuse member may also be supported on the substrate via one or more inter layers.
摘要翻译：一种用于半导体器件的微型保险丝。所述微型保险丝包括绝缘基底和细长金属保险丝构件，所述保险丝构件在所述基底上的任一端被支撑，并且包括至少一个熔融区域，所述至少一个保险丝区域与所述基底悬挂接触并成形为使得在使用中预定电流可以应用于它，使其不导通。可以在熔丝部件的熔断区域和绝缘体之间形成至少一个阻挡层。保险丝构件可以由容易氧化的金属形成，例如钛，钨，钽，铜或铝。保险丝构件可以具有两个或更多个保险丝区域，相邻保险丝区域之间的区域由金属轨道支撑。在这种情况下，熔丝部件也可以经由一个或多个层间被支撑在基板上。

2. 发明申请

WO2004096696A1 METHOD OF MANUFACTURING A MICRO-MECHANICAL ELEMENT 审中-公开
标题翻译：制造微机械元件的方法
公开(公告)号：WO2004096696A1
公开(公告)日：2004-11-11
申请号：PCT/GB2004/001773
申请日：2004-04-26
申请人： CAVENDISH KINETICS LTD , VAN KAMPEN, Robert , SMITH, Charles, Gordon , LUO, Jack , WEEKS, Andrew, John
发明人： VAN KAMPEN, Robert , SMITH, Charles, Gordon , LUO, Jack , WEEKS, Andrew, John
IPC分类号： B81B3/00
CPC分类号： B81C1/0015 , B81C2201/0109 , B81C2201/0132 , H01H59/0009
摘要： A method of manufacturing a micromechanical element wherein the method comprises the steps of providing a layer of base material, applying at least one at least partly sacrificial layer of an etchable material, patterning the at least partly sacrificial layer, to define at least a portion of the shape of the element, applying at least one structural layer of a mechanical material, patterning the structural layer to form at least a portion of the element, and removing at least partly the patterned at least partly sacrificial layer to release partly free the element. The mechanical material is selected from the group of conductive materials.
摘要翻译：一种制造微机械元件的方法，其中所述方法包括以下步骤：提供基材层，施加可蚀刻材料的至少一个至少部分牺牲层，图案化所述至少部分牺牲层，以限定至少部分牺牲层元件的形状，施加机械材料的至少一个结构层，图案化结构层以形成元件的至少一部分，以及至少部分去除图案化的至少部分牺牲层以释放部分地释放元件。机械材料选自导电材料组。

3. 发明申请

WO2007060415A1 A MICRO-ELECTROMECHANICAL SYSTEM MEMORY DEVICE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：微机电系统存储器件及其制造方法
公开(公告)号：WO2007060415A1
公开(公告)日：2007-05-31
申请号：PCT/GB2006/004353
申请日：2006-11-22
申请人： CAVENDISH KINETICS LIMITED , KAZINZCI, Robert , VAN KAMPEN, Robert , SMITH, Charles
发明人： KAZINZCI, Robert , VAN KAMPEN, Robert , SMITH, Charles
IPC分类号： G11C23/00 , B81B3/00
CPC分类号： B81C1/00666 , B81B3/001 , B81B2203/0118 , B81C2201/0109 , G11C23/00
摘要： A method of manufacturing a non-volatile memory bitcell comprises the steps of depositing a first layer of conductive material on a substrate and patterning and etching the first layer of conductive material to form three non-linearly disposed electrodes. The method also comprises the steps of depositing a first layer of sacrificial material on the electrodes and the substrate and providing an elongate cantilever structure on the first layer of sacrificial material such that the cantilever structure and at least a portion of each electrode overlap each other. The method also includes the steps of depositing a second layer of sacrificial material on the cantilever structure and the first layer of sacrificial material and providing a capping layer on the second layer of sacrificial material and providing holes in the capping layer such that at least a portion of the second layer of sacrificial material is exposed. Finally, the method provides the step of removing the first and second layers of sacrificial material through the holes provided in the capping layer, thereby defining a cavity in which the cantilever structure is suspended.
摘要翻译：一种制造非易失性存储器位单元的方法包括以下步骤：将第一层导电材料沉积在衬底上，并对第一层导电材料进行图案化和蚀刻以形成三个非线性布置的电极。该方法还包括以下步骤：在电极和衬底上沉积牺牲材料的第一层，并在第一牺牲材料层上提供细长的悬臂结构，使得悬臂结构和每个电极的至少一部分彼此重叠。该方法还包括以下步骤：将第二层牺牲材料沉积在悬臂结构和第一牺牲材料层上，并在牺牲材料的第二层上提供覆盖层，并在封盖层中提供孔，使得至少一部分的第二层牺牲材料被暴露。最后，该方法提供了通过设置在覆盖层中的孔去除第一层和第二层牺牲材料的步骤，从而限定悬臂悬臂结构的空腔。

4. 发明申请

WO2007060414A1 METHOD OF ENCLOSING A MICRO-ELECTROMECHANICAL ELEMENT 审中-公开
标题翻译：封装微电子元件的方法
公开(公告)号：WO2007060414A1
公开(公告)日：2007-05-31
申请号：PCT/GB2006/004350
申请日：2006-11-22
申请人： CAVENDISH KINETICS LIMITED , VAN KAMPEN, Robert , SMITH, Charles
发明人： VAN KAMPEN, Robert , SMITH, Charles
IPC分类号： B81C5/00 , H01L23/525
CPC分类号： B81C1/00333 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution.
摘要翻译：在互补金属氧化物半导体制造工艺中，制造包含微机电系统器件的分层壳体的方法，所述方法包括以下步骤：在所述壳体的至少一层中提供空腔，所述空腔可通过通孔在其上沉积的绝缘材料层中，并且绝缘材料层被导电材料的薄膜层覆盖。该方法还包括对空腔的内表面的至少一部分进行疏水处理的步骤。最后，该方法包括以下步骤：将晶片浸入电镀溶液中，并将导电层电镀到导电材料的薄膜层上，使得空腔保持不含电镀溶液。

5. 发明申请

WO2007052039A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：WO2007052039A1
公开(公告)日：2007-05-10
申请号：PCT/GB2006/004107
申请日：2006-11-02
申请人： CAVENDISH KINETICS LIMITED , VAN KAMPEN, Robert , KAZINCZI, Robert
发明人： VAN KAMPEN, Robert , KAZINCZI, Robert
IPC分类号： B81B3/00 , G11C23/00 , G11C11/50 , H01H1/00
CPC分类号： H01H59/0009 , B81C1/0015 , B81C2201/014 , B81C2201/0176 , G11C23/00 , H01H51/12
摘要： A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever (101) over at least a portion of the first layer of sacrificial material. The third step is depositing, by use of Atomic Layer Deposition, a second layer of sacrificial material over the first layer of sacrificial material and over a portion of the cantilever such that a portion of the cantilever is surrounded by sacrificial material. The fourth step is providing a further layer material (107) which covers at least a portion of the second layer of sacrificial material. Finally, the last step is etching away the sacrificial material surrounding the cantilever, thereby defining a cavity (102) in which the cantilever is suspended.
摘要翻译：一种非易失性存储器件和制造非易失性微机电存储单元的方法。该方法包括通过使用原子层沉积在衬底上沉积第一层牺牲材料的第一步骤。该方法的第二步是在第一牺牲材料层的至少一部分上提供悬臂（101）。第三步是通过使用原子层沉积在第一层牺牲材料上并在悬臂的一部分上沉积第二层牺牲材料，使得悬臂的一部分被牺牲材料包围。第四步是提供覆盖牺牲材料的第二层的至少一部分的另外的层材料（107）。最后，最后一步是蚀刻掉围绕悬臂的牺牲材料，由此限定悬臂悬挂在其中的空腔（102）。

6. 发明申请

WO2008032069A1 NON-VOLATILE MEMORY BITCELL 审中-公开
标题翻译：非易失性存储器BITCELL
公开(公告)号：WO2008032069A1
公开(公告)日：2008-03-20
申请号：PCT/GB2007/003470
申请日：2007-09-13
申请人： CAVENDISH KINETICS LIMITED , SCHEPENS, Cor , VAN KAMPEN, Robert
发明人： SCHEPENS, Cor , VAN KAMPEN, Robert
IPC分类号： G11C23/00
CPC分类号： G11C23/00 , G11C13/004 , G11C2013/0042
摘要： A non-volatile memory bitcell which comprises a first bistable cantilever module and a second bistable cantilever modules. The bistable cantilever modules have a shared output terminal and each has an input terminal and two actuating terminals. The first and second cantilever modules are arranged such that their states are complementary. The memory bitcell further includes buffering means arranged to prevent the flow of current from the shared output terminal and further arranged to indicate the states of the first and second cantilever modules.
摘要翻译：一种非易失性存储器位单元，包括第一双稳态悬臂模块和第二双稳态悬臂模块。双稳态悬臂模块具有共享输出端子，每个端子均具有输入端子和两个驱动端子。第一和第二悬臂模块被布置成使得它们的状态是互补的。存储器位单元还包括缓冲装置，其被布置成防止来自共享输出端子的电流流动，并进一步布置成指示第一和第二悬臂模块的状态。

7. 发明申请

WO2004075221A3 MICRO FUSE 审中-公开
标题翻译： MICRO保险丝
公开(公告)号：WO2004075221A3
公开(公告)日：2005-02-10
申请号：PCT/GB2004000655
申请日：2004-02-18
申请人： CAVENDISH KINETICS LTD , VAN KAMPEN ROBERT , SMITH CHARLES GORDON , KAZINSKI ROBERT
发明人： VAN KAMPEN ROBERT , SMITH CHARLES GORDON , KAZINSKI ROBERT
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A micro fuse for use in a semiconductor device. The micro fuse comprises an insulating substrate and an elongate metal fuse member, the fuse member being supported at either end on the substrate and including at least one fuse region suspended out of contact with the substrate and shaped such that, in use, a predetermined current can be applied to it to make it non-conducting. At least one barrier may be formed between the fuse region of the fuse member and the insulator. The fuse member may be formed from a readily oxidisable metal, such as Titanium, Tungsten, Tantalum, Copper or Aluminium. The fuse member may have two or more fuse regions, with a region between adjacent fuse regions being supported by a metal track. In this case, the fuse member may also be supported on the substrate via one or more inter layers.
摘要翻译：一种用于半导体器件的微型保险丝。微型熔断器包括绝缘基板和细长金属熔断元件，熔断元件在基板上的任一端被支撑，并且包括至少一个熔断器区域，该熔断器区域与衬底悬挂接触并成形为使得在使用中预定电流可以应用于它，使其不导通。可以在熔丝部件的熔断区域和绝缘体之间形成至少一个阻挡层。保险丝构件可以由容易氧化的金属形成，例如钛，钨，钽，铜或铝。保险丝构件可以具有两个或更多个保险丝区域，相邻保险丝区域之间的区域由金属轨道支撑。在这种情况下，熔丝部件也可以经由一个或多个内层被支撑在基板上。

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