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1. 发明申请

WO0051281A3 POWER CONSERVATION WITH A SYNCHRONOUS MASTER-SLAVE SERIAL DATA BUS 审中-公开
标题翻译：使用同步主从串行数据总线进行电源保护
公开(公告)号：WO0051281A3
公开(公告)日：2007-06-07
申请号：PCT/US0003958
申请日：2000-02-16
申请人： USAR SYSTEMS INC , WANG WEI , MARTEN VICTOR , MILIOS IOANNIS
发明人： WANG WEI , MARTEN VICTOR , MILIOS IOANNIS
IPC分类号： G06F1/26 , H04L1/18 , H04L7/00
CPC分类号： H04L7/0008 , H04L1/1803
摘要： A system is described in which the Master (52) can stop its clock (70) and go into a low-power state (for power conservation reasons) at arbitrary times. Before going into the stopped-clock or low-power mode, the Master (700 checks that the serial bus (50) is idle (defined as both Clock and Data lines being "High"). A latch circuit (81) is provided which is active when the master (52) is in low-power mode. The latch circuit (81) watches for the very first negative-going clock pulse (from the slave), and its configuration is such that when latched, it holds the clock line (70) low. Holding the clock line (70) low prompts the slave (51) to discontinue efforts to send the data. Stated differently, the slave (51) will not conclude that it had successfully sent its data, and this prompts the slave (51) to retain a copy of its data for later resending.
摘要翻译：描述了一种系统，其中主（52）可以在任意时间停止其时钟（70）并进入低功率状态（为了节能原因）。在进入停止时钟或低功耗模式之前，主器件（700）检查串行总线（50）是否空闲（定义为时钟和数据线都为“高”），提供一个锁存电路（81）当主器件（52）处于低功耗模式时，锁存电路（81）监视来自从器件的第一个负向时钟脉冲，并且其配置使得当锁存时，其保持时钟线路（70）为低电平，时钟线（70）低电平提示从机（51）停止发送数据，换句话说，从机（51）不会断定已经成功发送了数据，从属（51）保留其数据的副本以供稍后重新发送。

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