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1. 发明申请

WO2006067733A1 ON SILICON INTERCONNECT CAPACITANCE EXTRACTION 审中-公开
标题翻译：硅互连电容提取
公开(公告)号：WO2006067733A1
公开(公告)日：2006-06-29
申请号：PCT/IB2005/054320
申请日：2005-12-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , THEENDAKARA, Praveen , PELGROM, Marcel , WIELING, Jean, G. , VEENDRICK, Hendricus, J., M.
发明人： THEENDAKARA, Praveen , PELGROM, Marcel , WIELING, Jean, G. , VEENDRICK, Hendricus, J., M.
IPC分类号： G01R27/26 , G01R31/30
CPC分类号： G01R31/2853 , G01R27/2605
摘要： The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.
摘要翻译：本发明涉及用于硅互连电容（Cx）提取的片上电路，其被自身补偿以用于集成晶体管中的工艺变化。电路（10）包括信号产生装置（20），用于产生连接到第一和第二信号延迟装置（31,32）的周期性脉冲信号，用于各自延迟所述脉冲信号，其中所述第二信号延迟装置（32）被配置具有由所述互连电容（Cx）影响的延迟; 用于连接所述各个第一和第二延迟装置（31,32）的相应第一和第二延迟信号的逻辑异或门（35），所述逻辑异或门（35）连接到信号积分装置（40）; 并且所述信号积分装置（40）连接到模数转换装置（50）。虽然传统的无补偿系统中的误差，如延迟线，误差可高达30％，但在根据本发明的电路中，由于前端处理变化引起的误差约为2％。此外，以数字格式提供输出，因此可以用简单的外部硬件快速测量。此外，脉冲信号频率可以用作监视器来测量前端的过程变化。此外，由于电路（10）非常精确且非常容易测量，因此作为未来制造的每个芯片的过程监视器是最佳选择。

2. 发明申请

WO2007148268A3 SEMICONDUCTOR DEVICE WITH TEST STRUCTURE AND SEMICONDUCTOR DEVICE TEST METHOD 审中-公开
标题翻译：具有测试结构和半导体器件测试方法的半导体器件
公开(公告)号：WO2007148268A3
公开(公告)日：2008-04-24
申请号：PCT/IB2007052268
申请日：2007-06-14
申请人： NXP BV , PELGROM MARCEL , PETRESCU VIOLETA , THEENDAKARA PRAVEEN
发明人： PELGROM MARCEL , PETRESCU VIOLETA , THEENDAKARA PRAVEEN
IPC分类号： G01R31/30
CPC分类号： G01R31/2884 , G01R31/3161
摘要： The invention relates to a semiconductor device comprising a test structure (100) for detecting variations in the structure of the semiconductor device, the test structure (100) comprising a first supply rail (110), a second supply rail (120), a ring oscillator (130) coupled between the first supply rail (110) and second supply rail (120), the ring oscillator (130) having an output (132) for providing a test result signal, and an array (140) of individually controllable transistors (142) coupled in parallel between the first supply rail (110) and the ring oscillator (130). Variations in the current output of the respective transistors (142) in the array (140) lead to variations in the respective output frequencies of the ring oscillator (130). This gives a qualitative indication of the aforementioned structural variations. More accurate results can be obtained by inclusion of a reference current source (160) for calibrating the ring oscillator (130) prior to the measurement of the current output of the individual transistors (142).
摘要翻译：本发明涉及一种包括用于检测半导体器件结构变化的测试结构（100）的半导体器件，该测试结构（100）包括第一电源轨（110），第二电源轨（120），环耦合在第一电源轨道（110）和第二电源轨道（120）之间的振荡器（130），环形振荡器（130）具有用于提供测试结果信号的输出（132）和独立可控晶体管的阵列（140）（142），并联在所述第一电源轨（110）和所述环形振荡器（130）之间。阵列（140）中的相应晶体管（142）的电流输出的变化导致环形振荡器（130）的相应输出频率的变化。这给出了上述结构变化的定性指示。通过在测量各个晶体管（142）的电流输出之前，包括用于校准环形振荡器（130）的参考电流源（160）可以获得更准确的结果。

3. 发明申请

WO2007148268A2 SEMICONDUCTOR DEVICE WITH TEST STRUCTURE AND SEMICONDUCTOR DEVICE TEST METHOD 审中-公开
标题翻译：具有测试结构和半导体器件测试方法的半导体器件
公开(公告)号：WO2007148268A2
公开(公告)日：2007-12-27
申请号：PCT/IB2007/052268
申请日：2007-06-14
申请人： NXP B.V. , PELGROM, Marcel , PETRESCU, Violeta , THEENDAKARA, Praveen
发明人： PELGROM, Marcel , PETRESCU, Violeta , THEENDAKARA, Praveen
IPC分类号： G01R31/28
CPC分类号： G01R31/2884 , G01R31/3161
摘要： The invention relates to a semiconductor device comprising a test structure (100) for detecting variations in the structure of the semiconductor device, the test structure (100) comprising a first supply rail (110), a second supply rail (120), a ring oscillator (130) coupled between the first supply rail (110) and second supply rail (120), the ring oscillator (130) having an output (132) for providing a test result signal, and an array (140) of individually controllable transistors (142) coupled in parallel between the first supply rail (110) and the ring oscillator (130). Variations in the current output of the respective transistors (142) in the array (140) lead to variations in the respective output frequencies of the ring oscillator (130). This gives a qualitative indication of the aforementioned structural variations. More accurate results can be obtained by inclusion of a reference current source (160) for calibrating the ring oscillator (130) prior to the measurement of the current output of the individual transistors (142).
摘要翻译：本发明涉及一种包括用于检测半导体器件结构变化的测试结构（100）的半导体器件，该测试结构（100）包括第一电源轨（110），第二电源轨（120），环耦合在所述第一电源轨道（110）和第二电源轨道（120）之间的振荡器（130），所述环形振荡器（130）具有用于提供测试结果信号的输出（132）和独立可控晶体管的阵列（140）（142），并联在所述第一电源轨（110）和所述环形振荡器（130）之间。阵列（140）中的相应晶体管（142）的电流输出的变化导致环形振荡器（130）的相应输出频率的变化。这给出了上述结构变化的定性指示。通过在测量各个晶体管（142）的电流输出之前，包括用于校准环形振荡器（130）的参考电流源（160）可以获得更准确的结果。

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