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1. 发明申请

WO2012131701A3 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS FOR AERIAL VIEW DISPLAY 审中-公开
标题翻译：用于处理基于雷达的信号用于空中视频显示的FPGA系统
公开(公告)号：WO2012131701A3
公开(公告)日：2012-12-27
申请号：PCT/IN2012000161
申请日：2012-03-07
申请人： TATA POWER COMPANY LTD , DIKSHIT RAGHUKUL , REDDY PRADEEP
发明人： DIKSHIT RAGHUKUL , REDDY PRADEEP
IPC分类号： G06F17/10
CPC分类号： G01S7/298 , G01S7/032 , G01S7/12
摘要： A Field Programmable Gate Array (FPGA) system to read input radar signals and produce an output for plotting an aerial radar display on a pre-defined map to obtain a rendition of the position of a target being mapped. Analog radar signals received are converted to digital signals by an RSC. Received digital signal and radar control signal are used by PPI to create aerial scan video frames. The created frames are stored in a DDR2 SDRAM storage means via a DDR2 multiport controller having a pre-determined number of read/write ports, each port having a pre-defined priority. The created frames are positioned and resized in raster zoom-pan controller means and then blended with synthetic video generated by a host processor to produce a fused video by alpha blender using alpha blending technique. An alpha blender provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：现场可编程门阵列（FPGA）系统，用于读取输入的雷达信号，并产生一个输出，用于在预定义的地图上绘制空中雷达显示，以获得被映射目标的位置的再现。接收的模拟雷达信号通过RSC转换为数字信号。接收的数字信号和雷达控制信号被PPI用于创建航空扫描视频帧。创建的帧通过具有预定数量的读/写端口的DDR2多端口控制器存储在DDR2 SDRAM存储装置中，每个端口具有预定义的优先级。所创建的框架以光栅缩放平移控制器方式定位和调整大小，然后与由主机处理器生成的合成视频相混合，通过Alpha混合技术通过alpha混合器产生融合视频。 Alpha混合器提供非隔行扫描，以预定分辨率光栅显示融合视频。

2. 发明申请

WO2011080757A3 METHOD FOR ALIGNING AND POSITIONING A MODULE MOUNTED ON A VEHICLE 审中-公开
标题翻译：用于在车辆上安装的模块的对准和定位的方法
公开(公告)号：WO2011080757A3
公开(公告)日：2011-11-10
申请号：PCT/IN2010000856
申请日：2010-12-27
申请人： TATA POWER COMPANY LTD , VENKATASWAMY KISHORE KUMAR
发明人： VENKATASWAMY KISHORE KUMAR
IPC分类号： B60R11/00 , F16B1/00 , G12B5/00
CPC分类号： G01C9/00 , B60R11/00 , G01C5/04
摘要： A method for aligning and positioning a module mounted on a vehicle is provided in accordance with the present invention. Modules requiring azimuth and elevation position accuracy need to be aligned to be relatively horizontal (true to earth) for efficient operation. The method in accordance with this invention achieves this by providing an adaptor, typically a substantially flat plate element, on a vehicle frame for mounting the module. The vehicle frame is first aligned true to earth using a screw jack and an electronic sensor is calibrated with reference to the vehicle frame. Then the adaptor is aligned such that it is also true to earth. The module is fitted and locked on the leveled adapted plate. Hydraulic jacks are provided to adjust the vehicle frame and accordingly the adaptor to align true to earth irrespective of the type of terrain the vehicle is located on.
摘要翻译：根据本发明提供了一种用于对准和定位安装在车辆上的模块的方法。要求方位角和仰角位置精度的模块需要对齐成相对水平（真实地球），以实现有效的操作。根据本发明的方法通过在车架上提供用于安装模块的适配器（通常为基本平坦的板件）来实现这一点。车架首先使用螺丝千斤顶对准地球，电子传感器参照车架进行校准。然后适配器对齐，这样对地球也是如此。模块安装并锁定在调平板上。提供液压千斤顶以调整车架，并且相应地适配器将其与地面对准，而与车辆位于的地形类型无关。

3. 发明申请

WO2011077453A2 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS 审中-公开
标题翻译：用于处理基于雷达的信号的FPGA系统
公开(公告)号：WO2011077453A2
公开(公告)日：2011-06-30
申请号：PCT/IN2010/000833
申请日：2010-12-21
申请人： THE TATA POWER COMPANY LTD. , DIKSHIT, Raghukul Bhushan , REDDY, Pradeep N.
发明人： DIKSHIT, Raghukul Bhushan , REDDY, Pradeep N.
IPC分类号： G06F17/10
CPC分类号： G01S7/064 , G01S7/295
摘要： A Field Programmable Gate Array (FPGA) system is provided to read input radar signals and produce an output for plotting a regular radar display on a pre-defined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar. Analog radar signals received are converted to digital signals by an RSC. CFAR mechanism is used to condition the digital signals which are then compressed to create video frames by a B-Scope. The created video frames are stored in a DDR storage means via a DDR arbiter having a pre-determined number of read/write ports, each port having a pre-defined priority. The created video frames are blended with a synthetic video to produce a fused video by alpha blending technique. An alpha display provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：提供现场可编程门阵列（FPGA）系统来读取输入雷达信号并产生用于在预定义的地图上绘制规则雷达显示的输出，以获得准确和易于阅读再现由雷达映射的目标的位置。接收到的模拟雷达信号由RSC转换为数字信号。 CFAR机制用于调节数字信号，然后通过B-Scope对数字信号进行压缩以创建视频帧。通过具有预定数量的读/写端口的DDR仲裁器将创建的视频帧存储在DDR存储装置中，每个端口具有预定义的优先级。创建的视频帧与合成视频混合，通过alpha混合技术生成融合视频。字幕显示以预先确定的分辨率为融合视频的光栅显示提供非隔行扫描。

4. 发明申请

WO2011080757A2 METHOD FOR ALIGNING AND POSITIONING A MODULE MOUNTED ON A VEHICLE 审中-公开
标题翻译：对准和定位安装在车辆上的模块的方法
公开(公告)号：WO2011080757A2
公开(公告)日：2011-07-07
申请号：PCT/IN2010/000856
申请日：2010-12-27
申请人： THE TATA POWER COMPANY LTD. , VENKATASWAMY, Kishore Kumar
发明人： VENKATASWAMY, Kishore Kumar
CPC分类号： G01C9/00 , B60R11/00 , G01C5/04
摘要： A method for aligning and positioning a module mounted on a vehicle is provided in accordance with the present invention. Modules requiring azimuth and elevation position accuracy need to be aligned to be relatively horizontal (true to earth) for efficient operation. The method in accordance with this invention achieves this by providing an adaptor, typically a substantially flat plate element, on a vehicle frame for mounting the module. The vehicle frame is first aligned true to earth using a screw jack and an electronic sensor is calibrated with reference to the vehicle frame. Then the adaptor is aligned such that it is also true to earth. The module is fitted and locked on the leveled adapted plate. Hydraulic jacks are provided to adjust the vehicle frame and accordingly the adaptor to align true to earth irrespective of the type of terrain the vehicle is located on.
摘要翻译：根据本发明提供了一种用于对准和定位安装在车辆上的模块的方法。要求方位角和仰角位置准确度的模块需要对齐，以便相对水平（真实对地）以实现高效操作。根据本发明的方法通过在车辆框架上提供用于安装模块的适配器（通常为大致平坦的板元件）来实现这一点。首先使用螺旋千斤顶将车架与地面对齐，并且参照车架校准电子传感器。然后将适配器对齐，使其对地也是如此。模块安装并锁定在水平调整板上。提供液压千斤顶来调整车辆框架，并因此使适配器实现真实地对齐，而不管车辆所处的地形类型如何。

5. 发明申请

WO2014091442A2 SOLID BRICKS FOR CONSTRUCTION PURPOSE USING BOTTOM ASH AS MAIN INGREDIENT 审中-公开
标题翻译：使用底部ASH作为主要成分的建筑用途的固体砖
公开(公告)号：WO2014091442A2
公开(公告)日：2014-06-19
申请号：PCT/IB2013060851
申请日：2013-12-12
申请人： TATA POWER COMPANY LTD
发明人： BHASAGI DATTKUMAR IRASHETTEPPA , PAWASKAR UTTAM SHANKAR , RAILKAR PARAG ACHYUT
CPC分类号： C04B28/02 , Y02W30/92 , C04B18/06 , C04B18/08 , C04B40/0067 , C04B40/0071
摘要： A process of producing compressed block or bricks for use in building and construction is described herein. The process includes comprises the steps of providing bottom ash about 75% by weight, fly ash and cement, mixing the bottom ash, fly ash and cement to produce a mortar, moulding the mortar in a desired shape, and curing the moulded mortar. The usage of waste material produced by coal combustion to produce solid bricks to be used primarily for construction purposes. The bricks are produced by compressing bottom ash as the primary constituent with fly ash and cement to produce solid bricks having sufficient structural strength for use in building and construction. This present subject matter helps in reducing the problem of disposal of bottom ash that has very little use and causes environmental problem. The solid bricks prepared by the present method are an economical alternative in building construction which in turn help in reducing mining of natural soil used in conventional clay bricks.
摘要翻译：本文描述了一种制造用于建筑和施工的压块或砖的方法。该方法包括以下步骤：提供约75重量％的底灰，飞灰和水泥，混合底灰，飞灰和水泥以产生砂浆，将所需形状的砂浆成型，并固化模制的砂浆。煤燃烧生产的废料主要用于建筑用途的固体砖的使用。这些砖是通过将底灰作为主要成分与粉煤灰和水泥进行压制而生产的，以生产具有足够结构强度的固体砖，用于建筑和施工。本课题有助于减少使用量少，造成环境问题的底灰处理问题。通过本方法制备的固体砖是建筑施工的经济替代方案，这又有助于减少常规粘土砖中使用的天然土壤的开采。

6. 发明申请

WO2013114398A2 FPGA SYSTEM FOR USB BRIDGE IMPLEMENTATION 审中-公开
标题翻译：用于USB桥接器实现的FPGA系统
公开(公告)号：WO2013114398A2
公开(公告)日：2013-08-08
申请号：PCT/IN2013/000031
申请日：2013-01-17
申请人： THE TATA POWER COMPANY LTD. , DIKSHIT RAGHUKUL , JAIN AKANKSHA
发明人： DIKSHIT RAGHUKUL , JAIN AKANKSHA
IPC分类号： G06F15/80
CPC分类号： G06F13/4045 , Y02D10/14 , Y02D10/151
摘要： A Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device overcomes drawbacks known in the art including lack of security due to software based encryption implementation and driver and OS dependency. The USB bridge comprises a Host PHY operating in a Device mode and a Device PHY operating in a Host mode, connected to the USB Host and the USB mass storage device respectively via a bidirectional USB link. The FPGA is connected to each of the Host PHY and the Device PHY via a bidirectional ULPI link respectively. Data from the USB Host is written into the FPGA of the USB bridge through the Host PHY. This data in parallel form is then stored internally and subsequently communicated to the USB mass storage device through the Device PHY over the Device ULPI Interface.
摘要翻译：用于USB主机和USB大容量存储设备之间的数据通信的基于现场可编程门阵列（FPGA）的USB桥接实现克服了本领域已知的缺陷，包括由于基于软件的加密实现而导致的安全性不足和驱动程序和操作系统依赖性。 USB桥包括以设备模式运行的主机PHY和以主机模式运行的设备PHY，其分别通过双向USB链路连接到USB主机和USB大容量存储设备。 FPGA分别通过双向ULPI链路连接到每个主机PHY和设备PHY。来自USB主机的数据通过主机PHY写入USB桥的FPGA。然后将并行形式的这些数据存储在内部，并随后通过设备PHY通过设备ULPI接口传送到USB大容量存储设备。

7. 发明申请

WO2013114398A3 FPGA SYSTEM FOR USB BRIDGE IMPLEMENTATION 审中-公开
标题翻译：用于USB桥接实现的FPGA系统
公开(公告)号：WO2013114398A3
公开(公告)日：2013-10-10
申请号：PCT/IN2013000031
申请日：2013-01-17
申请人： TATA POWER COMPANY LTD , DIKSHIT RAGHUKUL , JAIN AKANKSHA
发明人： DIKSHIT RAGHUKUL , JAIN AKANKSHA
IPC分类号： G06F13/00
CPC分类号： G06F13/4045 , Y02D10/14 , Y02D10/151
摘要： A Field Programmable Gate Array (FPGA) based USB bridge implementation for communication of data between a USB Host and a USB mass storage device overcomes drawbacks known in the art including lack of security due to software based encryption implementation and driver and OS dependency. The USB bridge comprises a Host PHY operating in a Device mode and a Device PHY operating in a Host mode, connected to the USB Host and the USB mass storage device respectively via a bidirectional USB link. The FPGA is connected to each of the Host PHY and the Device PHY via a bidirectional ULPI link respectively. Data from the USB Host is written into the FPGA of the USB bridge through the Host PHY. This data in parallel form is then stored internally and subsequently communicated to the USB mass storage device through the Device PHY over the Device ULPI Interface.
摘要翻译：用于USB主机和USB大容量存储设备之间的数据通信的基于现场可编程门阵列（FPGA）的USB桥接实现克服了本领域已知的缺点，包括由于基于软件的加密实现和驱动器和OS依赖性而导致的安全性不足。 USB桥包括以设备模式操作的主机PHY和以主机模式操作的设备PHY，分别经由双向USB链路连接到USB主机和USB大容量存储设备。 FPGA分别通过双向ULPI链路连接到主机PHY和设备PHY中的每一个。 USB主机的数据通过主机PHY写入USB桥的FPGA。然后将并行形式的数据存储在内部，随后通过设备ULPI接口通过设备PHY传送到USB大容量存储设备。

8. 发明申请

WO2012131701A2 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS FOR AERIAL VIEW DISPLAY 审中-公开
标题翻译：用于处理基于雷达的信号用于空中视频显示的FPGA系统
公开(公告)号：WO2012131701A2
公开(公告)日：2012-10-04
申请号：PCT/IN2012/000161
申请日：2012-03-07
申请人： THE TATA POWER COMPANY LTD. , DIKSHIT, Raghukul , REDDY, Pradeep
发明人： DIKSHIT, Raghukul , REDDY, Pradeep
IPC分类号： G06F17/10
CPC分类号： G01S7/298 , G01S7/032 , G01S7/12
摘要： A Field Programmable Gate Array (FPGA) system to read input radar signals and produce an output for plotting an aerial radar display on a pre-defined map to obtain a rendition of the position of a target being mapped. Analog radar signals received are converted to digital signals by an RSC. Received digital signal and radar control signal are used by PPI to create aerial scan video frames. The created frames are stored in a DDR2 SDRAM storage means via a DDR2 multiport controller having a pre-determined number of read/write ports, each port having a pre-defined priority. The created frames are positioned and resized in raster zoom-pan controller means and then blended with synthetic video generated by a host processor to produce a fused video by alpha blender using alpha blending technique. An alpha blender provides non-interlaced scanning for raster display of the fused video at a pre¬ determined resolution.
摘要翻译：现场可编程门阵列（FPGA）系统，用于读取输入的雷达信号并产生输出，用于在预定义的地图上绘制空中雷达显示，以获得被映射的目标的位置的再现。接收的模拟雷达信号通过RSC转换成数字信号。接收的数字信号和雷达控制信号被PPI用于创建航空扫描视频帧。创建的帧通过具有预定数量的读/写端口的DDR2多端口控制器存储在DDR2 SDRAM存储装置中，每个端口具有预定义的优先级。创建的框架以光栅缩放平移控制器的方式定位和调整大小，然后与由主机处理器生成的合成视频相混合，通过Alpha混合技术通过alpha混合器产生融合视频。 Alpha混合器以预定的分辨率为融合视频的光栅显示提供非隔行扫描。

9. 发明申请

WO2011077453A3 FPGA SYSTEM FOR PROCESSING RADAR BASED SIGNALS 审中-公开
标题翻译：用于处理基于雷达信号的FPGA系统
公开(公告)号：WO2011077453A3
公开(公告)日：2011-10-06
申请号：PCT/IN2010000833
申请日：2010-12-21
申请人： TATA POWER COMPANY LTD , DIKSHIT RAGHUKUL BHUSHAN , REDDY PRADEEP N
发明人： DIKSHIT RAGHUKUL BHUSHAN , REDDY PRADEEP N
IPC分类号： G06F17/10
CPC分类号： G01S7/064 , G01S7/295
摘要： A Field Programmable Gate Array (FPGA) system is provided to read input radar signals and produce an output for plotting a regular radar display on a pre-defined map to obtain an accurate and easy-to-read rendition of the position of a target being mapped by the radar. Analog radar signals received are converted to digital signals by an RSC. CFAR mechanism is used to condition the digital signals which are then compressed to create video frames by a B-Scope. The created video frames are stored in a DDR storage means via a DDR arbiter having a pre-determined number of read/write ports, each port having a pre-defined priority. The created video frames are blended with a synthetic video to produce a fused video by alpha blending technique. An alpha display provides non-interlaced scanning for raster display of the fused video at a pre-determined resolution.
摘要翻译：提供现场可编程门阵列（FPGA）系统来读取输入的雷达信号并产生一个输出，用于在预定义的地图上绘制常规的雷达显示，以获得准确和易于阅读的目标位置的演示由雷达映射接收的模拟雷达信号通过RSC转换为数字信号。 CFAR机制用于调节数字信号，然后通过B-Scope压缩数字信号以创建视频帧。所创建的视频帧通过具有预定数量的读/写端口的DDR仲裁器存储在DDR存储装置中，每个端口具有预定义的优先级。所创建的视频帧与合成视频混合，通过alpha混合技术产生融合视频。阿尔法显示器以预定分辨率提供非隔行扫描以对融合视频进行光栅显示。

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