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1. 发明申请

WO2009015306A2 CAPACITOR SAVE ENERGY VERIFICATION 审中-公开
标题翻译：电容器节省能源验证
公开(公告)号：WO2009015306A2
公开(公告)日：2009-01-29
申请号：PCT/US2008071106
申请日：2008-07-25
申请人： AGIGA TECH INC , SARTORE RONALD
发明人： SARTORE RONALD
IPC分类号： H02J15/00
CPC分类号： G11C14/00 , G11C5/141 , G11C16/30
摘要： A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.
摘要翻译：存储器子系统被配置为从外部系统和至少一个功率电容器获得电力。存储器子系统包括验证功率电容器的功率输送能力的逻辑。

2. 发明申请

WO2009015306A3 CAPACITOR SAVE ENERGY VERIFICATION 审中-公开
公开(公告)号：WO2009015306A3
公开(公告)日：2009-01-29
申请号：PCT/US2008/071106
申请日：2008-07-25
申请人： AGIGA TECH INC , SARTORE, Ronald
发明人： SARTORE, Ronald
IPC分类号： G11C11/00
摘要： A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.

3. 发明申请

WO2007059364A3 SPREAD SPECTRUM CLOCK FOR USB 审中-公开
标题翻译：用于USB的扩展频谱时钟
公开(公告)号：WO2007059364A3
公开(公告)日：2008-05-29
申请号：PCT/US2006060111
申请日：2006-10-20
申请人： CYPRESS SEMICONDUCTOR CORP , SARTORE RONALD H , WILLIAMS TIMOTHY J
发明人： SARTORE RONALD H , WILLIAMS TIMOTHY J
IPC分类号： H03B5/00
CPC分类号： G06F1/04
摘要： A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a clock to the transmission frequency during a packet exchange and tuning the clock to one or more frequencies within a second frequency range after the packet exchange. The clock may be variably tuned to multiple frequencies within either the first or second range.
摘要翻译：一种用于产生时钟信号的方法，装置或系统，其包括确定用于接收或发送数据流的第一频率范围内的传输频率，在分组交换期间将时钟锁定到传输频率并将时钟调谐到一个或多个频率在分组交换之后的第二频率范围内。时钟可以在第一或第二范围内可变地调谐到多个频率。

4. 发明申请

WO2009015309A1 POWER INTERRUPT RECOVERY IN A HYBRID MEMORY SUBSYSTEM 审中-公开
标题翻译：混合存储器子系统中的功率中断恢复
公开(公告)号：WO2009015309A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071110
申请日：2008-07-25
申请人： AGIGA TECH INC , SARTORE, Ronald
发明人： SARTORE, Ronald
IPC分类号： G11C5/14
CPC分类号： G06F12/0638 , G11C5/143 , G11C5/144 , Y02D10/13
摘要： A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.
摘要翻译：存储器子系统包括易失性存储器和非易失性存储器，以及用于在检测到系统电源的恢复时中断存储器子系统的掉电保存操作的逻辑，并且如果足够的非易失性存储器容量内存子系统可用于备份内存子系统的易失性内存容量。

5. 发明申请

WO2009015310A1 VARIABLE PARTITIONING IN A HYBRID MEMORY SUBSYSTEM 审中-公开
标题翻译：混合存储器子系统中的可变分配
公开(公告)号：WO2009015310A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071112
申请日：2008-07-25
申请人： AGIGA TECH INC , SARTORE, Ronald
发明人： SARTORE, Ronald
IPC分类号： G11C5/14
CPC分类号： G06F12/0638 , G06F11/1441 , G06F11/1451 , G06F13/4239 , G11C5/143 , G11C5/144
摘要： A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.
摘要翻译：存储器子系统可以包括逻辑，使得可以向其安装易失性存储器的至少一部分的设备提供可用于在设备电源故障的情况下被备份到非易失性存储器的设备。该逻辑可能使设备在易失性存储器的至少一部分可用于在设备电源故障的情况下不被备份到非易失性存储器，并且使该设备至少一部分非易失性存储器是可用的不保留用于来自易失性存储器的备份。

6. 发明申请

WO2009015285A1 HYBRID NONVOLATILE RAM 审中-公开
标题翻译：混合非易失性RAM
公开(公告)号：WO2009015285A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071051
申请日：2008-07-24
申请人： AGIGA TECH INC , SARTORE, Ronald
发明人： SARTORE, Ronald
IPC分类号： G06F12/00
CPC分类号： G06F11/1458 , G06F1/30 , G06F1/305 , G06F12/023 , G06F12/0638 , G06F12/0868 , G06F12/0871 , G11C7/10 , G11C11/005 , Y02D10/13
摘要： A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
摘要翻译：存储器子系统包括易失性存储器，非易失性存储器和包括将易失性存储器连接到外部系统的逻辑的控制器。易失性存储器可寻址以供外部系统读写。存储器子系统包括具有逻辑的功率控制器，用于检测从外部系统到易失性和非易失性存储器中的至少一个以及控制器的功率是否失效。当外部系统电源发生故障时，将备用电源提供给易失性和非易失性存储器中的至少一个以及控制器足够长以使得控制器能够将数据从易失性存储器备份到非易失性存储器。

7. 发明申请

WO2007059364A2 SPREAD SPECTRUM CLOCK FOR USB 审中-公开
标题翻译：用于USB的扩展频谱时钟
公开(公告)号：WO2007059364A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/060111
申请日：2006-10-20
申请人： CYPRESS SEMICONDUCTOR CORPORATION , SARTORE, Ronald, H. , WILLIAMS, Timothy, J.
发明人： SARTORE, Ronald, H. , WILLIAMS, Timothy, J.
IPC分类号： H04L5/16
CPC分类号： G06F1/04
摘要： A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a clock to the transmission frequency during a packet exchange and tuning the clock to one or more frequencies within a second frequency range after the packet exchange. The clock may be variably tuned to multiple frequencies within either the first or second range.
摘要翻译：一种用于产生时钟信号的方法，装置或系统，其包括确定用于接收或发送数据流的第一频率范围内的传输频率，在分组交换期间将时钟锁定到传输频率，并将时钟调谐到一个或多个频率在分组交换之后的第二频率范围内。时钟可以在第一或第二范围内可变地调谐到多个频率。

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