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1. 发明申请

WO2007121452A2 BRANCHING AND BEHAVIORAL PARTITIONING FOR A VLIW PROCESSOR 审中-公开
标题翻译： VLIW处理器的分支和行为分配
公开(公告)号：WO2007121452A2
公开(公告)日：2007-10-25
申请号：PCT/US2007/066813
申请日：2007-04-17
申请人： LIGA SYSTEMS, INC. , VERHEYEN, Henry, T. , SAHAI, Paraminder, S. , WATT, William , COLWILL, Paul
发明人： VERHEYEN, Henry, T. , SAHAI, Paraminder, S. , WATT, William , COLWILL, Paul
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027
摘要： In one aspect, the present invention overcomes the limitations of the prior art by providing a logic simulation system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.
摘要翻译：在一个方面，本发明通过提供一种使用具有多个并行处理器元件的VLIW仿真处理器来加速可合成任务的仿真的逻辑仿真系统来克服现有技术的限制，但也支持非可合成任务和/或分支。在一种方法中，VLIW模拟处理器基于不具有片上指令高速缓存的架构。相反，直接从程序存储器和各个处理器元件的VLIW指令字流基于指令字被连续编程。这也允许有效地实施侧入口跳跃，其中可以在区域中间输入代码区域，而不是总是需要从顶部进入。另一方面，非可合成任务可以由异常处理程序有效地处理。

2. 发明申请

WO2007121452A3 BRANCHING AND BEHAVIORAL PARTITIONING FOR A VLIW PROCESSOR 审中-公开
标题翻译： VLIW处理器的分支和行为分配
公开(公告)号：WO2007121452A3
公开(公告)日：2008-05-02
申请号：PCT/US2007066813
申请日：2007-04-17
申请人： LIGA SYSTEMS INC , VERHEYEN HENRY T , SAHAI PARAMINDER S , WATT WILLIAM , COLWILL PAUL
发明人： VERHEYEN HENRY T , SAHAI PARAMINDER S , WATT WILLIAM , COLWILL PAUL
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F17/5027
摘要： In one aspect, the present invention overcomes the limitations of the prior art by providing a logic simulation system that uses a VLIW simulation processor with many parallel processor elements to accelerate the simulation of synthesizable tasks but that also supports non-synthesizable tasks and/or branching. In one approach, the VLIW simulation processor is based on an architecture that does not have an on-chip instruction cache. Instead, VLIW instruction words stream in directly from a program memory and the individual processor elements are programmed continuously based on the instruction words. This also allows the efficient implementation of side-entrance jumps, where a region of code can be entered in the middle of the region rather than always requiring entrance from the top. In another aspect, non-synthesizable tasks can be efficiently handled by exception handlers.
摘要翻译：在一个方面，本发明通过提供一种使用具有多个并行处理器元件的VLIW仿真处理器来加速可合成任务的仿真的逻辑仿真系统来克服现有技术的限制，但也支持非可合成任务和/或分支。在一种方法中，VLIW模拟处理器基于不具有片上指令高速缓存的架构。相反，直接从程序存储器和各个处理器元件的VLIW指令字流基于指令字被连续编程。这也允许有效地实施侧入口跳跃，其中可以在区域中间输入代码区域，而不是总是需要从顶部进入。另一方面，非可合成任务可以由异常处理程序有效地处理。

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