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1. 发明申请

WO2006081150A9 SYSTEM AND METHOD FOR PERFORMING CONCATENATION OF DIVERSELY ROUTED CHANNELS 审中-公开
标题翻译：用于执行多径路由通道的系统和方法
公开(公告)号：WO2006081150A9
公开(公告)日：2008-01-17
申请号：PCT/US2006002144
申请日：2006-01-20
申请人： RAZA MICROELECTRONICS INC , NARVAEZ PAOLO , BOG MURAT
发明人： NARVAEZ PAOLO , BOG MURAT
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H04L49/552 , H04J3/062 , H04J3/12 , H04J3/1611 , H04J3/1617 , H04J2203/0069 , H04J2203/0085 , H04J2203/0094 , H04L12/54 , H04L49/351
摘要： A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de- sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de- sequencing control commands received from the LCAS control manager.
摘要翻译：提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，该系统具有数据对准器，其被配置为根据成员组来对齐输入数据的字节。该系统还包括LCAS控制管理器，其被配置为响应于来自数据对准器的数据输入而生成去排序控制命令。该系统进一步包括解调器，其被配置为根据从LCAS控制管理器接收的解码控制命令来对从数据对准器输入的输入数据进行解调。

2. 发明申请

WO2005013061A3 ADVANCED PROCESSOR 审中-公开
标题翻译：先进的处理器
公开(公告)号：WO2005013061A3
公开(公告)日：2005-12-08
申请号：PCT/US2004023871
申请日：2004-07-23
申请人： RAZA MICROELECTRONICS INC , HASS DAVID T , ZAIDI NAZAR A , RASHID ABBAS , MUKHERJEE BASAB , KAZA ROHINI KRISHNA , RAMIREZ RICARDO
发明人： HASS DAVID T , ZAIDI NAZAR A , RASHID ABBAS , MUKHERJEE BASAB , KAZA ROHINI KRISHNA , RAMIREZ RICARDO
IPC分类号： G06F12/08 , H04L12/56 , G06F15/16 , G06F9/30 , G06F12/00
CPC分类号： H04L49/15 , G06F12/0813
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个多线程处理器核心，每个处理器核心具有数据高速缓存和指令高速缓存。数据交换互连耦合到每个处理器核心并被配置为在处理器核心之间传递信息。消息传送网络耦合到每个处理器内核和多个通信端口。在本发明实施例的一个方面中，数据交换互连通过其各自的数据高速缓存耦合到每个处理器核，并且消息传递网络通过其各自的消息站被耦合到每个处理器核。本发明的优点包括以有效且成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

3. 发明申请

WO2006081150A3 SYSTEM AND METHOD FOR PERFORMING CONCATENATION OF DIVERSELY ROUTED CHANNELS 审中-公开
标题翻译：用于执行多径路由通道的系统和方法
公开(公告)号：WO2006081150A3
公开(公告)日：2009-04-09
申请号：PCT/US2006002144
申请日：2006-01-20
申请人： RAZA MICROELECTRONICS INC , NARVAEZ PAOLO , BOG MURAT
发明人： NARVAEZ PAOLO , BOG MURAT
IPC分类号： H04B7/216
CPC分类号： H04L49/552 , H04J3/062 , H04J3/12 , H04J3/1611 , H04J3/1617 , H04J2203/0069 , H04J2203/0085 , H04J2203/0094 , H04L12/54 , H04L49/351
摘要： A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de- sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de- sequencing control commands received from the LCAS control manager.
摘要翻译：提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，该系统具有数据对准器，其被配置为根据成员组来对齐输入数据的字节。该系统还包括LCAS控制管理器，其被配置为响应于来自数据对准器的数据输入而生成去排序控制命令。该系统进一步包括解调器，其被配置为根据从LCAS控制管理器接收的解码控制命令来对从数据对准器输入的输入数据进行解调。

4. 发明申请

WO2006104804A3 MECHANISM FOR MANAGING ACCESS TO RESOURCES IN A HETEROGENEOUS DATA REDIRECTION DEVICE 审中-公开
公开(公告)号：WO2006104804A3
公开(公告)日：2006-10-05
申请号：PCT/US2006/010401
申请日：2006-03-21
申请人： RAZA MICROELECTRONICS, INC. , NARVAEZ, Paolo , BOG, Murat
发明人： NARVAEZ, Paolo , BOG, Murat
IPC分类号： H04L12/26
摘要： A system and method for policing of access to resources in a heterogeneous data redirection device is discloses. The invention utilizes Random Early Detection to determine whether or not a given packet should be dropped or accepted into the resource (312, 322, 332). The invention uses a combination of different metrics (340) each of which utilizes a different of REC. Schemes can include a Per-Flow Weighted RED metric, a Global RED metric and a Fair Share Pool metric, where shared resource allocation is dependent dynamically upon the number of users at the time a packet request access. These metrics can be combined in variety of ways to yield a final drop or accept decision for an incoming packet so that it does not access resources.

5. 发明申请

WO2006081150A8 SYSTEM AND METHOD FOR PERFORMING CONCATENATION OF DIVERSELY ROUTED CHANNELS 审中-公开
标题翻译：用于执行多径路由通道的系统和方法
公开(公告)号：WO2006081150A8
公开(公告)日：2007-07-12
申请号：PCT/US2006002144
申请日：2006-01-20
申请人： RAZA MICROELECTRONICS INC , NARVAEZ PAOLO , BOG MURAT
发明人： NARVAEZ PAOLO , BOG MURAT
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H04L49/552 , H04J3/062 , H04J3/12 , H04J3/1611 , H04J3/1617 , H04J2203/0069 , H04J2203/0085 , H04J2203/0094 , H04L12/54 , H04L49/351
摘要： A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de- sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de- sequencing control commands received from the LCAS control manager.
摘要翻译：提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，该系统具有数据对准器，其被配置为根据成员组来对齐输入数据的字节。该系统还包括LCAS控制管理器，其被配置为响应于来自数据对准器的数据输入而生成去排序控制命令。该系统进一步包括解调器，其被配置为根据从LCAS控制管理器接收的解码控制命令来对从数据对准器输入的输入数据进行解调。

6. 发明申请

WO2006104804A2 MECHANISM FOR MANAGING ACCESS TO RESOURCES IN A HETEROGENEOUS DATA REDIRECTION DEVICE 审中-公开
标题翻译：用于管理异构数据重定向设备中资源的机制
公开(公告)号：WO2006104804A2
公开(公告)日：2006-10-05
申请号：PCT/US2006010401
申请日：2006-03-21
申请人： RAZA MICROELECTRONICS INC , NARVAEZ PAOLO , BOG MURAT
发明人： NARVAEZ PAOLO , BOG MURAT
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L47/10 , H04L47/2441 , H04L47/30 , H04L47/326 , H04L47/6215 , H04L49/90 , H04L49/9047
摘要： A system and method for policing of access to resources in a heterogeneous data redirection device is disclosed. The invention utilizes Random Early Detection to determine whether or not a given packet should be dropped or accepted into the resource. The invention uses a combination of different metrics each of which utilizes a different version of RED. Schemes can include a Per-Flow Weighted RED metric, a Global RED metric and a Fair Share Pool metric, where shared resource allocation is dependent dynamically upon the number of users at the time a packet requests access. These metrics can be combined in variety of ways to yield a final drop or accept decision for an incoming packet so that it does not access resources.
摘要翻译：公开了一种用于在异构数据重定向设备中对资源的访问进行管理的系统和方法。本发明利用随机早期检测来确定给定的分组是否应被丢弃或接受到资源中。本发明使用不同的度量的组合，其中每个都使用不同版本的RED。方案可以包括每流加权RED度量，全球RED度量和公平共享池度量，其中共享资源分配在动态上依赖于数据包请求访问时的用户数量。这些度量可以通过多种方式进行组合，以产生最终丢弃或接受传入数据包的决定，从而不访问资源。

7. 发明申请

WO2004068314A2 METHOD AND DEVICE FOR THE CLASSIFICATION AND REDIRECTION OF DATA PACKETS IN A HETEROGENEOUS NETWORK 审中-公开
标题翻译：数据分组在异构网络中的分类和重定向的方法和设备
公开(公告)号：WO2004068314A2
公开(公告)日：2004-08-12
申请号：PCT/US2004/002399
申请日：2004-01-27
申请人： RAZA MICROELECTRONICS, INC. , NARVAEZ, Paolo
发明人： NARVAEZ, Paolo
IPC分类号： G06F
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/2408 , H04L47/31
摘要： A system and method for classification of data units in a network device acts as a bridge in heterogeneous networks, provides many different services and provisions many different transport mechanisms. The data classifier generates an ID that is internally used by the network device in managing, queuing, processing, scheduling and routing to egress the data unit. This internal ID enables the device to accept any type of data units from any physical/logical ports or channels and output those data units on any physical/logical ports or channels that are available. The device utilizes learning on a per-flow basis and can enable the device to identify and process data units used in private line services and private LAN services.
摘要翻译：用于网络设备中数据单元分类的系统和方法在异构网络中充当桥梁，提供许多不同的服务，并提供许多不同的传输机制。数据分类器生成内部由网络设备用于管理，排队，处理，调度和路由以出口数据单元的ID。该内部ID使设备能够从任何物理/逻辑端口或通道接收任何类型的数据单元，并在可用的任何物理/逻辑端口或通道上输出这些数据单元。该设备利用基于每流的学习，并且可以使设备识别和处理在专线服务和专用LAN服务中使用的数据单元。

8. 发明申请

WO2006081150A2 SYSTEM AND METHOD FOR PERFORMING CONCATENATION OF DIVERSELY ROUTED CHANNELS 审中-公开
标题翻译：用于执行多径路由通道的系统和方法
公开(公告)号：WO2006081150A2
公开(公告)日：2006-08-03
申请号：PCT/US2006/002144
申请日：2006-01-20
申请人： RAZA MICROELECTRONICS, INC. , NARVAEZ, Paolo , BOG, Murat
发明人： NARVAEZ, Paolo , BOG, Murat
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H04L49/552 , H04J3/062 , H04J3/12 , H04J3/1611 , H04J3/1617 , H04J2203/0069 , H04J2203/0085 , H04J2203/0094 , H04L12/54 , H04L49/351
摘要： A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de- sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de- sequencing control commands received from the LCAS control manager.
摘要翻译：提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，所述系统具有数据对准器，其被配置为根据成员组对齐输入数据的字节。该系统还包括LCAS控制管理器，其被配置为响应于从数据对准器输入的数据来生成去排序控制命令。该系统还包括一个去序列发生器，其被配置为根据从LCAS控制管理器接收的解码控制命令对从数据对准器输入的输入数据进行排序。

9. 发明申请

WO2005013061A2 ADVANCED PROCESSOR 审中-公开
标题翻译：高级处理器
公开(公告)号：WO2005013061A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/023871
申请日：2004-07-23
申请人： RAZA MICROELECTRONICS, INC. , HASS, David, T. , ZAIDI, Nazar, A. , RASHID, Abbas , MUKHERJEE, Basab , KAZA, Rohini, Krishna , RAMIREZ, Ricardo
发明人： HASS, David, T. , ZAIDI, Nazar, A. , RASHID, Abbas , MUKHERJEE, Basab , KAZA, Rohini, Krishna , RAMIREZ, Ricardo
IPC分类号： G06F
CPC分类号： H04L49/15 , G06F12/0813
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

10. 发明申请

WO2007038431A3 SCALEABLE CHANNEL SCHEDULER SYSTEM AND METHOD 审中-公开
标题翻译：可扩展信道调度系统和方法
公开(公告)号：WO2007038431A3
公开(公告)日：2007-11-29
申请号：PCT/US2006037252
申请日：2006-09-25
申请人： RAZA MICROELECTRONICS , NARVAEZ PAOLO
发明人： NARVAEZ PAOLO
IPC分类号： A61B17/08
CPC分类号： H04L47/10 , H04L12/1881 , H04L47/20 , H04L47/215 , H04L47/2441 , H04L47/50 , H04L47/527 , H04L47/623
摘要： A data flow egress scheduler and shaper provides multiple levels of scheduling for data packets exiting communications devices. A classifier separates data from multiple sources by data flow and by priority within a data flow. An output controller requests a data packet for transmission and the scheduler selects a next available highest priority packet from a next in sequence data flow or from a management data queue. The shaper can control the rates of classes of service to be scheduled by the device. The scheduler typically comprises three levels of scheduling. Large numbers of output ports can be implemented in a single device by a virtual scheduler that services each data flow, output port and data source as a shared component, maintain context for groups of schedulers and data flows.
摘要翻译：数据流出口调度器和整形器为离开通信设备的数据分组提供多级调度。分类器通过数据流和数据流中的优先级将数据从多个源分离。输出控制器请求数据分组进行传输，并且调度器从顺序数据流中的下一个或从管理数据队列中选择下一个可用的最高优先级分组。整形器可以控制设备预定的服务等级的速率。调度器通常包括三个调度级别。大量输出端口可以通过虚拟调度程序在单个设备中实现，该调度程序将每个数据流，输出端口和数据源作为共享组件提供服务，为调度程序和数据流组维护上下文。

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