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1. 发明申请

WO2011036214A1 A MEMORY DEVICE AND A METHOD OF MANUFACTURING THE MEMORY DEVICE 审中-公开
标题翻译：一种存储器件和一种制造存储器件的方法
公开(公告)号：WO2011036214A1
公开(公告)日：2011-03-31
申请号：PCT/EP2010/064060
申请日：2010-09-23
申请人： UNIVERSITÉ CATHOLIQUE DE LOUVAIN , TANG, Xiaohui , RASKIN, Jean-Pierre
发明人： TANG, Xiaohui , RASKIN, Jean-Pierre
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/788 , G11C16/04
CPC分类号： H01L21/28273 , B82Y10/00 , G11C11/5621 , G11C16/0408 , G11C2216/06 , H01L29/42324 , H01L29/42332 , H01L29/66825 , H01L29/7883 , H01L29/7887
摘要： A semiconductor memory device is provided with a source and a drain electrode between which a channel extends, one, two or more nano floating gates overlying said channel, and a control gate. It is manufactured in that an insulating substrate is provided with an alternating layer stack of a first and a second semiconductor material, for instance Si/SiGe/Si/SiGe/Si/BOX or Si/SiGe/Si/BOX stacks. The alternating layer stack is patterned down to the insulating substrate according to a predefined pattern including the source electrode, the drain electrode and a channel region extending between said electrodes. The patterned alternating layer stack is then oxidized, such that the second semiconductor material in the channel region is completely oxidized under certain conditions to separate the channel from the floating gates made of first semiconductor material or the second semiconductor material agglomerates under other conditions to form one of the floating gates. The semiconductor memory device preferably comprises a first and a second floating gate on top of each other, which are self-aligned with said channel. The present technology makes it possible to realize multil-bit memory cells and qubit quantum computers.
摘要翻译：半导体存储器件设置有源极和漏极，沟道延伸在其之间，覆盖所述沟道的一个，两个或更多个纳米浮动栅极和控制栅极。制造的绝缘基板设置有第一和第二半导体材料的交替层叠，例如Si / SiGe / Si / SiGe / Si / BOX或Si / SiGe / Si / BOX堆叠。根据包括源电极，漏极电极和在所述电极之间延伸的沟道区域的预定图案，将交替层叠层图案化成绝缘基板。图案化的交替层堆叠然后被氧化，使得沟道区域中的第二半导体材料在某些条件下被完全氧化，以将沟道与由其它条件下的第一半导体材料或第二半导体材料聚集的浮动栅极分离以形成一个的浮动门。半导体存储器件优选地包括彼此顶部的第一和第二浮置栅极，其与所述沟道自对准。本技术使得可以实现多位存储单元和量子位量子计算机。

2. 发明申请

WO2008098993A2 IMPOSING AND DETERMINING STRESS IN SUB-MICRON SAMPLES 审中-公开
标题翻译：在亚微米样品中施加和确定应力
公开(公告)号：WO2008098993A2
公开(公告)日：2008-08-21
申请号：PCT/EP2008/051810
申请日：2008-02-14
申请人： UNIVERSITE CATHOLIQUE DE LOUVAIN , PARDOEN, Thomas , RASKIN, Jean-Pierre , CARBONNELLE, Pierre , GRAVIER, Sébastien
发明人： PARDOEN, Thomas , RASKIN, Jean-Pierre , CARBONNELLE, Pierre , GRAVIER, Sébastien
IPC分类号： G01L5/00
CPC分类号： G01L5/0047 , G01L5/18
摘要： This invention provides a method and device for imposing and determining mechanical stress and/or strain, on micro-scale and nano-scale beams, films or multi-layers of materials such as metallic materials, polymer materials, ceramic materials, carbon-based materials and silicon-based materials using a set of micro- or nano-machines. The present invention also provides methods to derive and modify various properties or state of such nano- or microstructures, among others mechanical properties, and to measure the external stimulus that they are subjected to.
摘要翻译：本发明提供了一种用于施加和确定机械应力和/或应变的方法和装置，所述方法和装置在微米级和纳米级的射束，膜或多层材料如金属材料，聚合物材料，陶瓷材料，碳基材料和使用一套微米或纳米机器的硅基材料。本发明还提供了衍生和修饰这些纳米或微米结构的各种性质或状态以及其他机械性质，并测量它们所经受的外部刺激的方法。

3. 发明申请

WO2007093018A2 INTERNAL STRESS ACTUATED MICRO- AND NANOMACHINES FOR TESTING PHYSICAL PROPERTIES OF MICRO AND NANO-SIZED MATERIAL SAMPLES 审中-公开
标题翻译：内部应力激励的微米和纳米材料用于测试微米和纳米尺寸材料样品的物理性能
公开(公告)号：WO2007093018A2
公开(公告)日：2007-08-23
申请号：PCT/BE2007/000017
申请日：2007-02-14
申请人： UNIVERSITÉ CATHOLIQUE DE LOUVAIN , PARDOEN, Thomas , FABRÈGUE, Damien , RASKIN, Jean-Pierre , ANDRÉ, Nicolas , COULOMBIER, Michaël
发明人： PARDOEN, Thomas , FABRÈGUE, Damien , RASKIN, Jean-Pierre , ANDRÉ, Nicolas , COULOMBIER, Michaël
CPC分类号： G01L5/0047 , G01L5/18 , Y10T29/4913 , Y10T29/49865
摘要： This invention provides an internal stress actuated micro- or nano- machine for measuring mechanical and/or electrical properties, e.g. traction measurement, compression measurement or shear measurement, on micro- scale and nano-scale films or multi-layers of materials such as metallic materials, carbon-based materials and silicon-base materials. The device of the invention has applications in materials production industry, as well as in micro-electronics and for surface treatments and functionalization.
摘要翻译：本发明提供了一种用于测量机械和/或电特性的内应力致动的微米或纳米机器，例如，牵引测量，压缩测量或剪切测量，微米级和纳米级薄膜或多层材料如金属材料，碳基材料和硅基材料。本发明的装置在材料生产工业中以及在微电子学中以及用于表面处理和功能化方面具有应用。

4. 发明申请

WO2007082745A1 SELECTIVE ETCHING FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择性蚀刻
公开(公告)号：WO2007082745A1
公开(公告)日：2007-07-26
申请号：PCT/EP2007/000413
申请日：2007-01-18
申请人： UNIVERSITE CATHOLIQUE DE LOUVAIN , CHARAVEL, Rémy, Pascal, Henri , RASKIN, Jean-Pierre, Emmanuel, Octave, Ghislain
发明人： CHARAVEL, Rémy, Pascal, Henri , RASKIN, Jean-Pierre, Emmanuel, Octave, Ghislain
IPC分类号： H01L21/311 , H01L21/336 , B81C1/00
CPC分类号： H01L21/31116 , B81B2203/0118 , B81C1/00595 , H01L29/78648
摘要： A manufacturing process involves ion implantation (120) of selected parts of a SiO 2 layer, and vapour HF etching (140) to remove the selected ion implanted parts at a rate greater than the rate of removal of the other parts. By using ion implantation combined with a vapour etchant, the selectivity of the etching of the SiO 2 can be increased to 200. Such selectivity can lead to more precise manufacturing of structures, or simpler or more cost effective manufacturing. The ion implantation can have a nuclear deposited energy larger than 2 x 10 24 eV/cm 3 to break sufficient SiO 2 bonds. Enhancement of the etching selectivity can make implanted oxide a candidate for a sacrificial layer for MEMS devices or for buried mask definition, or for manufacturing mutually self aligned trenches for gates of double gate MOS transistors.
摘要翻译：制造方法涉及SiO 2层的选定部分的离子注入（120）和蒸气HF蚀刻（140），以以大于除去速率的速率除去选定的离子注入部件其他部分。通过使用与蒸气蚀刻剂结合的离子注入，可以将SiO 2的蚀刻的选择性提高到200.这种选择性可以导致更精确的结构制造，或更简单或更成本有效的制造。离子注入可以具有大于2×10 24 eV / cm 3的核沉积能量以破坏足够的SiO 2键。蚀刻选择性的增强可以使注入的氧化物成为用于MEMS器件的牺牲层或掩模掩模定义的候选，或用于制造用于双栅极MOS晶体管的栅极的相互自对准的沟槽。

5. 发明申请

WO2005031842A2 METHOD OF MANUFACTURING A MULTILAYER SEMICONDUCTOR STRUCTURE WITH REDUCED OHMIC LOSSES 审中-公开
标题翻译：用减少的OHMIC损失制造多层半导体结构的方法
公开(公告)号：WO2005031842A2
公开(公告)日：2005-04-07
申请号：PCT/BE2004/000137
申请日：2004-09-27
申请人： UNIVERSITE CATHOLIQUE DE LOUVAIN , LEDERER, Dimitri , RASKIN, Jean-Pierre
发明人： LEDERER, Dimitri , RASKIN, Jean-Pierre
IPC分类号： H01L21/322
CPC分类号： H01P3/006 , H01L21/76254 , H01L2223/6627 , H01L2924/1903
摘要： The present invention provides a method of manufacturing a multilayer semiconductor structure featuring reduced ohmic losses with respect to standard multilayer semiconductor structures. The semiconductor structure comprises a high resistivity silicon substrate with resistivity higher than 3 KΩ.cm, an active semiconductor layer and an insulating layer in between the silicon substrate and the active semiconductor layer. The method comprises suppressing ohmic losses inside the high resistivity silicon substrate by increasing, with regard to prior art devices, charge trap density between the insulating layer and the silicon substrate. In particular this may be obtained by applying an intermediate layer in between the silicon substrate and the insulating layer, the intermediate layer comprising grains having a size, wherein the mean size of the grains of the intermediate layer is smaller than 150 nm, preferably smaller than 50 nm.
摘要翻译：本发明提供一种制造相对于标准多层半导体结构而具有降低的欧姆损耗的多层半导体结构的方法。半导体结构包括电阻率高于3Kohhm·cm的高电阻率硅衬底，有源半导体层和位于硅衬底和有源半导体层之间的绝缘层。该方法包括通过相对于现有技术的器件增加绝缘层和硅衬底之间的电荷陷阱密度来抑制高电阻率硅衬底内的欧姆损耗。特别地，这可以通过在硅衬底和绝缘层之间施加中间层而获得，中间层包括具有尺寸的晶粒，其中中间层的晶粒的平均尺寸小于150nm，优选小于 50nm。

6. 发明申请

WO2008098993A9 IMPOSING AND DETERMINING STRESS IN SUB-MICRON SAMPLES 审中-公开
公开(公告)号：WO2008098993A9
公开(公告)日：2008-08-21
申请号：PCT/EP2008/051810
申请日：2008-02-14
申请人： UNIVERSITE CATHOLIQUE DE LOUVAIN , PARDOEN, Thomas , RASKIN, Jean-Pierre , CARBONNELLE, Pierre , GRAVIER, Sébastien
发明人： PARDOEN, Thomas , RASKIN, Jean-Pierre , CARBONNELLE, Pierre , GRAVIER, Sébastien
IPC分类号： G01L5/00 , G01L5/18
摘要： This invention provides a method and device for imposing and determining mechanical stress and/or strain, on micro-scale and nano-scale beams, films or multi-layers of materials such as metallic materials, polymer materials, ceramic materials, carbon-based materials and silicon-based materials using a set of micro- or nano-machines. The present invention also provides methods to derive and modify various properties or state of such nano- or microstructures, among others mechanical properties, and to measure the external stimulus that they are subjected to.

7. 发明申请

WO2008098993A3 IMPOSING AND DETERMINING STRESS IN SUB-MICRON SAMPLES 审中-公开
公开(公告)号：WO2008098993A3
公开(公告)日：2008-08-21
申请号：PCT/EP2008/051810
申请日：2008-02-14
申请人： UNIVERSITE CATHOLIQUE DE LOUVAIN , PARDOEN, Thomas , RASKIN, Jean-Pierre , CARBONNELLE, Pierre , GRAVIER, Sébastien
发明人： PARDOEN, Thomas , RASKIN, Jean-Pierre , CARBONNELLE, Pierre , GRAVIER, Sébastien
IPC分类号： G01L5/00 , G01L5/18
摘要： This invention provides a method and device for imposing and determining mechanical stress and/or strain, on micro-scale and nano-scale beams, films or multi-layers of materials such as metallic materials, polymer materials, ceramic materials, carbon-based materials and silicon-based materials using a set of micro- or nano-machines. The present invention also provides methods to derive and modify various properties or state of such nano- or microstructures, among others mechanical properties, and to measure the external stimulus that they are subjected to.

8. 发明申请

WO2005031842A3 METHOD OF MANUFACTURING A MULTILAYER SEMICONDUCTOR STRUCTURE WITH REDUCED OHMIC LOSSES 审中-公开
标题翻译：制造具有减少的欧姆损耗的多层半导体结构的方法
公开(公告)号：WO2005031842A3
公开(公告)日：2005-05-12
申请号：PCT/BE2004000137
申请日：2004-09-27
申请人： UNIV LOUVAIN , LEDERER DIMITRI , RASKIN JEAN-PIERRE
发明人： LEDERER DIMITRI , RASKIN JEAN-PIERRE
IPC分类号： H01L21/762 , H01P3/00
CPC分类号： H01P3/006 , H01L21/76254 , H01L2223/6627 , H01L2924/1903
摘要： The present invention provides a method of manufacturing a multilayer semiconductor structure featuring reduced ohmic losses with respect to standard multilayer semiconductor structures. The semiconductor structure comprises a high resistivity silicon substrate with resistivity higher than 3 Kohm.cm, an active semiconductor layer and an insulating layer in between the silicon substrate and the active semiconductor layer. The method comprises suppressing ohmic losses inside the high resistivity silicon substrate by increasing, with regard to prior art devices, charge trap density between the insulating layer and the silicon substrate. In particular this may be obtained by applying an intermediate layer in between the silicon substrate and the insulating layer, the intermediate layer comprising grains having a size, wherein the mean size of the grains of the intermediate layer is smaller than 150 nm, preferably smaller than 50 nm.
摘要翻译：本发明提供了一种制造相对于标准多层半导体结构具有减小的欧姆损耗的多层半导体结构的方法。该半导体结构包括电阻率高于3Kohm.cm的高电阻率硅衬底，有源半导体层以及位于硅衬底和有源半导体层之间的绝缘层。该方法包括通过相对于现有技术器件增加绝缘层和硅衬底之间的电荷陷阱密度来抑制高电阻率硅衬底内的欧姆损耗。具体地，这可以通过在硅基底和绝缘层之间施加中间层来获得，中间层包括具有尺寸的晶粒，其中中间层的晶粒的平均尺寸小于150nm，优选小于 50纳米。

9. 发明申请

WO2007093018A3 INTERNAL STRESS ACTUATED MICRO- AND NANOMACHINES FOR TESTING PHYSICAL PROPERTIES OF MICRO AND NANO-SIZED MATERIAL SAMPLES 审中-公开
标题翻译：用于测试微米和纳米尺寸材料样品的物理性能的内应力微动和纳米级
公开(公告)号：WO2007093018A3
公开(公告)日：2007-11-08
申请号：PCT/BE2007000017
申请日：2007-02-14
申请人： UNIV LOUVAIN , PARDOEN THOMAS , FABREGUE DAMIEN , RASKIN JEAN-PIERRE , ANDRE NICOLAS , COULOMBIER MICHAEL
发明人： PARDOEN THOMAS , FABREGUE DAMIEN , RASKIN JEAN-PIERRE , ANDRE NICOLAS , COULOMBIER MICHAEL
IPC分类号： G01L5/00
CPC分类号： G01L5/0047 , G01L5/18 , Y10T29/4913 , Y10T29/49865
摘要： This invention provides an internal stress actuated micro- or nano- machine for measuring mechanical and/or electrical properties, e.g. traction measurement, compression measurement or shear measurement, on micro- scale and nano-scale films or multi-layers of materials such as metallic materials, carbon-based materials and silicon-base materials. The device of the invention has applications in materials production industry, as well as in micro-electronics and for surface treatments and functionalization.
摘要翻译：本发明提供了用于测量机械和/或电特性的内部应力致动微型或纳米机器，例如。牵引测量，压缩测量或剪切测量，在微尺度和纳米级膜或多层材料如金属材料，碳基材料和硅基材料上。本发明的装置在材料生产行业以及微电子和表面处理和功能化方面都有应用。

10. 发明申请

WO2005031853A1 PROCESS FOR MANUFACTURING A MULTILAYER STRUCTURE MADE FROM SEMICONDUCTING MATERIALS 审中-公开
标题翻译：从半导体材料制造多层结构的工艺
公开(公告)号：WO2005031853A1
公开(公告)日：2005-04-07
申请号：PCT/IB2004/003340
申请日：2004-09-27
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , UNIVERSITE CATHOLIQUE DE LOUVAIN , RASKIN, Jean-Pierre , LEDERER, Dimitri , BRUNIER, François , PONCHAUT, Sylvie
发明人： RASKIN, Jean-Pierre , LEDERER, Dimitri , BRUNIER, François , PONCHAUT, Sylvie
IPC分类号： H01L21/762
CPC分类号： H01P3/006 , H01L21/76254 , H01L2223/6627 , H01L2924/1903
摘要： The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials and comprising an active layer, a support layer and an electrically insulating layer between the active layer and the support layer, characterised in that the process comprises modification of the density of carrier traps and / or the electrical charge within the electrically insulating layer, in order to minimise electrical losses in the structure support layer.
摘要翻译：本发明涉及用于制造由半导体材料制成的多层结构的方法，该方法包括有源层，支撑层和有源层与支撑层之间的电绝缘层，其特征在于该方法包括改变载体的密度捕获和/或电绝缘层内的电荷，以便最小化结构支撑层中的电损耗。

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