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1. 发明申请

WO2013063358A3 DIGITAL ERROR CORRECTION IN AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：模拟数字转换器中的数字错误校正
公开(公告)号：WO2013063358A3
公开(公告)日：2013-07-11
申请号：PCT/US2012062060
申请日：2012-10-26
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , MILER JOHN EARLE , PAYNE ROBERT FLOYD
发明人： MILER JOHN EARLE , PAYNE ROBERT FLOYD
IPC分类号： H03M1/12
CPC分类号： H03M1/0687 , H03M1/167
摘要： An analog-to-digital converter (ADC) (15) provides digital error correction. Parallel ADC stages are synchronously clocked to convert an analog input signal (A IN) into digital words; at least one of the digital outputs (D OUT) is encoded according to an error correction code. Decision logic circuitry (24) decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry (24) can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.
摘要翻译：模数转换器（ADC）（15）提供数字纠错。并行ADC级同步时钟，将模拟输入信号（A IN）转换为数字字; 数字输出（D OUT）中的至少一个根据纠错码进行编码。判决逻辑电路（24）对由并行级的数字输出的级联组成的码字进行解码，以导出数字输出，从该数字输出可以导出与模拟输入信号对应的数字输出字。对于系统代码，判决逻辑电路（24）可以提供用于校正来自ADC级之一的数字输出的一个或多个位的状态的误差信号; 或者，判决逻辑电路可以直接解码码字以提供数字输出。该架构可以应用于流水线ADC中的阶段。

2. 发明申请

WO2008109861A1 LOW NOISE CODING FOR DIGITAL DATA INTERFACE 审中-公开
标题翻译：数字数据接口的低噪声编码
公开(公告)号：WO2008109861A1
公开(公告)日：2008-09-12
申请号：PCT/US2008/056298
申请日：2008-03-07
申请人： TEXAS INSTRUMENTS INCORPORATED , CORSI, Marco , PAYNE, Robert, Floyd
发明人： CORSI, Marco , PAYNE, Robert, Floyd
IPC分类号： H03M1/00
CPC分类号： H03M9/00 , H04L25/14
摘要： A digital data interface system (150) comprises a data transmitter (152) configured to transmit a data word across a plurality of data lines (156). The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder (158) configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.
摘要翻译：数字数据接口系统（150）包括数据发送器（152），其被配置为跨多个数据线（156）发送数据字。数据字可以包括具有从最低位数到最高位数的位数顺序的多个数字数据位，具有较高噪声含量的最低有序位数和具有较高谐波含量的最高有序位数。该系统还包括编码器（158），其被配置为将多个数字数据位排列为串行数据集，以由数据发送器在多个数据线中的每一条上传输，其中至少一个串行化数据集的连续数据位匹配使得具有较高谐波含量的比特与较高噪声内容的比特匹配以基本上减轻数据字的噪声内容和谐波内容中的至少一个。

3. 发明申请

WO2013063358A2 DIGITAL ERROR CORRECTION IN AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：数模转换器中的数字误差校正
公开(公告)号：WO2013063358A2
公开(公告)日：2013-05-02
申请号：PCT/US2012/062060
申请日：2012-10-26
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , MILER, John Earle , PAYNE, Robert Floyd
发明人： MILER, John Earle , PAYNE, Robert Floyd
IPC分类号： H03M1/12
CPC分类号： H03M1/0687 , H03M1/167
摘要： An analog-to-digital converter (ADC) (15) provides digital error correction. Parallel ADC stages are synchronously clocked to convert an analog input signal (A IN) into digital words; at least one of the digital outputs (D OUT) is encoded according to an error correction code. Decision logic circuitry (24) decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry (24) can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.
摘要翻译：模数转换器（ADC）（15）提供数字误差校正。并行ADC级同步时钟将模拟输入信号（A IN）转换为数字字; 根据纠错码对至少一个数字输出（D OUT）进行编码。判定逻辑电路（24）对包括来自并行级的数字输出级联的码字进行解码，以导出数字输出，从该数字输出可导出对应于模拟输入信号的数字输出字。对于系统码的情况，判定逻辑电路（24）可以提供用于校正来自ADC级之一的数字输出的一个或多个比特的状态的误差信号; 或者，决策逻辑电路可以直接解码码字以提供数字输出。该架构可能适用于流水线ADC中的阶段。

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