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1. 发明申请

WO2007086204A1 DOUBLE GATE ISOLATION STRUCTURE FOR CCDS AND CORRESPONDING FABRICATING METHOD 审中-公开
标题翻译： CCDS和相应制造方法的双门隔离结构
公开(公告)号：WO2007086204A1
公开(公告)日：2007-08-02
申请号：PCT/JP2006/324790
申请日：2006-12-06
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , NIISOE, Naoto , HIRATA, Kazuhisa , YAMADA, Toru
发明人： NIISOE, Naoto , HIRATA, Kazuhisa , YAMADA, Toru
IPC分类号： H01L29/768 , H01L27/148 , H01L27/146 , H01L21/339 , H01L27/105
CPC分类号： H01L27/1057 , H01L27/14683 , H01L27/14831 , H01L29/66954 , H01L29/76833
摘要： A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
摘要翻译：在半导体衬底（101）上形成第一氧化膜（102）。第一氮化物膜（103）形成在第一氧化膜（102）的第一栅电极形成区上。多个第一栅电极（104）设置在第一氮化物膜（103）上，以彼此间隔开预定距离。第二氧化膜（105）覆盖每个第一栅电极（104）的上部和侧壁。第三氧化物膜的侧壁间隔物（106）被埋在由第二氧化膜（105）覆盖的每个第一栅极（104）的每个侧壁上产生的悬垂部分中。第二氮化物膜（107）覆盖位于第一栅极（104）之间的第二氧化物膜（105），侧壁间隔物（106）和第一氧化物膜（102）的一部分。在位于相邻的两个第一栅电极（104）之间的第二氮化物膜（107）的至少一部分上形成多个第二栅电极（108）。

2. 发明申请

WO2007086203A1 DOUBLE GATE ISOLATION STRUCTURE FOR CCDS AND CORRESPONDING FABRICATING METHOD 审中-公开
标题翻译： CCDS和相应制造方法的双门隔离结构
公开(公告)号：WO2007086203A1
公开(公告)日：2007-08-02
申请号：PCT/JP2006/324789
申请日：2006-12-06
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , NIISOE, Naoto , HIRATA, Kazuhisa , YAMADA, Toru
发明人： NIISOE, Naoto , HIRATA, Kazuhisa , YAMADA, Toru
IPC分类号： H01L29/768 , H01L21/339 , H01L27/146 , H01L27/148 , H01L27/105
CPC分类号： H01L29/66954 , H01L27/14683 , H01L27/14812 , H01L27/14831 , H01L29/76833
摘要： A first oxide film (102) and a first nitride film (103) are formed over a semiconductor substrate (101) so as to be stacked in this order. A plurality of first gate electrodes (104) are arranged on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. Upper part and side walls of each of the first gate electrode (104) is covered by a second oxide film (105). The second oxide film (105) and part of the first nitride film (103) located between the first gate electrodes (104) are covered by the second nitride film (106). A plurality of second gate electrodes (107) are formed on at least part of the second nitride film (106) located between adjacent two of the first gate electrodes (104). Each of the second gate electrodes (107) is separated from the first gate electrode (104) by the second oxide film (105) and the second nitride film (106) and separated from the semiconductor substrate (101) by the first oxide film (102), the first nitride film (103) and the second nitride film (106).
摘要翻译：在半导体衬底（101）上形成第一氧化膜（102）和第一氮化物膜（103），以便按顺序堆叠。多个第一栅极电极（104）被布置在第一氮化物膜（103）上以彼此间隔开预定的距离。第一栅电极（104）中的每一个的上部和侧壁被第二氧化膜（105）覆盖。位于第一栅电极（104）之间的第二氧化物膜（105）和第一氮化物膜（103）的一部分被第二氮化物膜（106）覆盖。在位于相邻的两个第一栅电极（104）之间的第二氮化物膜（106）的至少一部分上形成多个第二栅电极（107）。通过第二氧化膜（105）和第二氮化物膜（106）将第二栅极电极（107）与第一栅电极（104）分离，并且通过第一氧化膜（105）与半导体衬底 102），第一氮化物膜（103）和第二氮化物膜（106）。

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