专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2016012976A2 CHARGE STORAGE FERROELECTRIC MEMORY HYBRID AND ERASE SCHEME 审中-公开
标题翻译：电荷存储铁电存储器混合擦除方案
公开(公告)号：WO2016012976A2
公开(公告)日：2016-01-28
申请号：PCT/IB2015/055594
申请日：2015-07-23
申请人： NAMLAB GGMBH
发明人： MÜLLER, Stefan Ferdinand
IPC分类号： G11C11/22
CPC分类号： G11C11/2275 , G11C11/221 , G11C11/223 , G11C16/04 , H01L27/115 , H01L27/11585 , H01L29/78391
摘要： A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.
摘要翻译：描述了用于擦除包括包括FeFET的多个存储器单元的铁电场效应晶体管（FeFET）存储器电路的技术。每个FeFET包括栅极叠层，源极，漏极，沟道和体衬底区域，其中栅极叠层包括栅极和设置在栅极和沟道之间的铁电层。取决于通道类型，将正电压或负电压施加到至少一个FeFET存储器单元的源极和漏极区域。在将正电压施加到FeFET存储器单元的源极和漏极区期间，栅极和体衬底区域保持在接地状态，以引起至少一个FeFET存储器单元的擦除。另外，FeFET被描述为具有与栅极叠层内的铁电层相邻设置的电荷存储层。

2. 发明申请

WO2016012976A3 CHARGE STORAGE FERROELECTRIC MEMORY HYBRID AND ERASE SCHEME 审中-公开
标题翻译：充电储存电磁记忆混合和擦除方案
公开(公告)号：WO2016012976A3
公开(公告)日：2016-04-28
申请号：PCT/IB2015055594
申请日：2015-07-23
申请人： NAMLAB GGMBH
发明人： MÜLLER STEFAN FERDINAND
IPC分类号： G11C11/22
CPC分类号： G11C11/2275 , G11C11/221 , G11C11/223 , G11C16/04 , H01L27/115 , H01L27/11585 , H01L29/78391
摘要： A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.
摘要翻译：描述了一种用于擦除包括包含FeFET的多个存储单元的铁电场效应晶体管（FeFET）存储电路的技术。每个FeFET包括栅极堆叠，源极，漏极，沟道和体衬底区域，其中栅极堆叠包括栅极和布置在栅极和沟道之间的铁电层。根据通道类型，正电压或负电压施加到至少一个FeFET存储单元的源区和漏区。在将正电压施加到FeFET存储单元的源极和漏极区域时，栅极和体基板区域保持在基态，以引起至少一个FeFET存储单元的擦除。此外，描述了与栅极堆叠内的铁电层相邻设置的电荷存储层的FeFET。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式