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1. 发明申请

WO2006001915A2 SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开
标题翻译：具有多个半导体层的半导体器件
公开(公告)号：WO2006001915A2
公开(公告)日：2006-01-05
申请号：PCT/US2005016253
申请日：2005-05-11
申请人： FREESCALE SEMICONDUCTOR INC , VENKATESAN SURESH , FOISY MARK C , MENDICINO MICHAEL A , ORLOWSKI MARIUS K
发明人： VENKATESAN SURESH , FOISY MARK C , MENDICINO MICHAEL A , ORLOWSKI MARIUS K
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203
摘要： A semiconductor device structure (10) uses two semiconductor layers (16 & 20) to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors (38) when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors (40) preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers (16 & 20), both the N and P channel transistors (38 & 40) can be optimized for carrier mobility.
摘要翻译：半导体器件结构（10）使用两个半导体层（16和20）分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。用于确定它的导电特性是半导体的材料类型，晶面，取向和应变的组合。当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管（38）的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。或者，晶面可以是（111），在这种情况下的取向是不重要的。用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管（40）优选具有拉伸应变，硅半导体材料和（100）平面。利用分离的半导体层（16和20），N和P沟道晶体管（38和40）都可以针对载流子迁移率进行优化。

2. 发明申请

WO2005020279A3 SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES AND METHOD THEREFOR 审中-公开
标题翻译：具有从相对侧进行电接触的半导体器件及其方法
公开(公告)号：WO2005020279A3
公开(公告)日：2005-07-21
申请号：PCT/US2004022437
申请日：2004-07-13
申请人： FREESCALE SEMICONDUCTOR INC , SANCHEZ HECTOR , MENDICINO MICHAEL A , MIN BYOUNG W , YU KATHLEEN C
发明人： SANCHEZ HECTOR , MENDICINO MICHAEL A , MIN BYOUNG W , YU KATHLEEN C
IPC分类号： H01L21/02 , H01L21/768 , H01L21/84 , H01L23/48 , H01L23/522 , H01L27/06 , H01L27/12 , H01L21/8242 , H01L21/20 , H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的诸如电容器（75,77,79）的直接下面的无源器件，99）。通孔或导电区域（52）接触晶体管的扩散区或源极区（22）的底表面并接触第一电容器电极（75）。横向设置的垂直通孔（32,54,68）和互连（99）接触第二电容器电极（79）。金属互连或导电材料（68）可以用作通过在晶体管下方实现电源平面而不是邻近晶体管来节省电路面积的电源平面。

3. 发明申请

WO2006023159A2 TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A WIDTH DIRECTION AND METHOD THEREOF 审中-公开
标题翻译：具有应力变形和电容降低特性的晶体管结构在宽度方向及其方法
公开(公告)号：WO2006023159A2
公开(公告)日：2006-03-02
申请号：PCT/US2005024769
申请日：2005-07-15
申请人： FREESCALE SEMICONDUCTOR INC , CHEN JIAN , MENDICINO MICHAEL A , ADAMS VANCE H , YEAP CHOH-FEI , KOLAGUNTA VENKAT R
发明人： CHEN JIAN , MENDICINO MICHAEL A , ADAMS VANCE H , YEAP CHOH-FEI , KOLAGUNTA VENKAT R
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： A transistor (50) comprises a source (72) and drain (74) positioned within an active region (52). A gate (54) overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature (58, 60) extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.
摘要翻译：晶体管（50）包括位于有源区（52）内的源极（72）和漏极（74）。栅极（54）覆盖有源区域的沟道区域，其中沟道区域分离源极和漏极。晶体管还包括至少一个应力调节器和从源极到漏极延伸并且在栅极下方的电容减小特征（58,60），用于减小与栅极，源极和漏极相关联的电容。所述至少一个应力调节剂和电容还原特征包括电介质并且包括至少部分地由有源区限定的形状。

4. 发明申请

WO2005020279A2 SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES AND METHOD THEREFOR 审中-公开
标题翻译：具有电气接触的半导体器件及其方法
公开(公告)号：WO2005020279A2
公开(公告)日：2005-03-03
申请号：PCT/US2004/022437
申请日：2004-07-13
申请人： FREESCALE SEMICONDUCTOR, INC. , SANCHEZ, Hector , MENDICINO, Michael, A. , MIN, Byoung, W. , YU, Kathleen, C.
发明人： SANCHEZ, Hector , MENDICINO, Michael, A. , MIN, Byoung, W. , YU, Kathleen, C.
IPC分类号： H01L
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连件（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并接触电容器电极的第一（75）。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。可以使用金属互连或导电材料（68）作为通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

5. 发明申请

WO2006023185A2 TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A CHANNEL DIRECTION AND METHOD THEREOF 审中-公开
标题翻译：通道方向应力修正和容性降低的晶体管结构及其方法
公开(公告)号：WO2006023185A2
公开(公告)日：2006-03-02
申请号：PCT/US2005/025538
申请日：2005-07-15
申请人： FREESCALE SEMICONDUCTOR, INC. , CHEN, Jian , MENDICINO, Michael, A. , ADAMS, Vance, H. , YEAP, Choh-Fei , KOLAGUNTA, Venkat, R.
发明人： CHEN, Jian , MENDICINO, Michael, A. , ADAMS, Vance, H. , YEAP, Choh-Fei , KOLAGUNTA, Venkat, R.
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/78 , H01L29/7843
摘要： A transistor (40) comprises an active region having a periphery with opposing sides and a source (44) and a drain (42) positioned within the active region. A gate (46) overlies a channel area of the active region, the channel region separating the source (44) and drain (42). The transistor (40) further includes at least one stress modifying feature (54) extending from an edge of the active region on at least one of a source side or a drain side and toward the channel area but not entering the channel area. The at least one stress modifying feature (54) includes a dielectric.
摘要翻译：晶体管（40）包括有源区和有源区（44），漏极（42）位于有源区内，有源区具有带有相对侧的外围。栅极（46）覆盖有源区域的沟道区域，沟道区域分隔源极（44）和漏极（42）。晶体管（40）还包括至少一个应力修改特征（54），所述至少一个应力修改特征在源极侧或漏极侧中的至少一个上从有源区的边缘延伸并朝向沟道区但不进入沟道区。该至少一个应力修改特征（54）包括电介质。

6. 发明申请

WO2006023159A3 TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A WIDTH DIRECTION AND METHOD THEREOF 审中-公开
公开(公告)号：WO2006023159A3
公开(公告)日：2006-03-02
申请号：PCT/US2005/024769
申请日：2005-07-15
申请人： FREESCALE SEMICONDUCTOR, INC. , CHEN, Jian , MENDICINO, Michael, A. , ADAMS, Vance, H. , YEAP, Choh-Fei , KOLAGUNTA, Venkat, R.
发明人： CHEN, Jian , MENDICINO, Michael, A. , ADAMS, Vance, H. , YEAP, Choh-Fei , KOLAGUNTA, Venkat, R.
IPC分类号： H01L29/76 , H01L21/336
摘要： A transistor (50) comprises a source (72) and drain (74) positioned within an active region (52). A gate (54) overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature (58, 60) extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.

7. 发明申请

WO2006001915A3 SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开
公开(公告)号：WO2006001915A3
公开(公告)日：2006-01-05
申请号：PCT/US2005/016253
申请日：2005-05-11
申请人： FREESCALE SEMICONDUCTOR, INC. , VENKATESAN, Suresh , FOISY, Mark, C. , MENDICINO, Michael, A. , ORLOWSKI, Marius, K.
发明人： VENKATESAN, Suresh , FOISY, Mark, C. , MENDICINO, Michael, A. , ORLOWSKI, Marius, K.
IPC分类号： H01L29/04
摘要： A semiconductor device structure (10) uses two semiconductor layers (16 & 20) to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors (38) when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors (40) preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers (16 & 20), both the N and P channel transistors (38 & 40) can be optimized for carrier mobility.

8. 发明申请

WO2006023185A3 TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A CHANNEL DIRECTION AND METHOD THEREOF 审中-公开
标题翻译：具有应力修正和电容降低特性的晶体管结构在通道方向及其方法
公开(公告)号：WO2006023185A3
公开(公告)日：2006-09-28
申请号：PCT/US2005025538
申请日：2005-07-15
申请人： FREESCALE SEMICONDUCTOR INC , CHEN JIAN , MENDICINO MICHAEL A , ADAMS VANCE H , YEAP CHOH-FEI , KOLAGUNTA VENKAT R
发明人： CHEN JIAN , MENDICINO MICHAEL A , ADAMS VANCE H , YEAP CHOH-FEI , KOLAGUNTA VENKAT R
IPC分类号： H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/78 , H01L29/7843
摘要： A transistor (40) comprises an active region having a periphery with opposing sides and a source (44) and a drain (42) positioned within the active region. A gate (46) overlies a channel area of the active region, the channel region separating the source (44) and drain (42). The transistor (40) further includes at least one stress modifying feature (54) extending from an edge of the active region on at least one of a source side or a drain side and toward the channel area but not entering the channel area. The at least one stress modifying feature (54) includes a dielectric.
摘要翻译：晶体管（40）包括具有相对侧边缘的有源区和位于有源区内的源极（44）和漏极（42）。栅极（46）覆盖有源区域的沟道区域，沟道区域分离源极（44）和漏极（42）。晶体管（40）还包括至少一个应力调整特征（54），其从源极侧或漏极侧中的至少一个上的有源区域的边缘延伸并且朝向沟道区域而不进入沟道区域。所述至少一个应力改变特征（54）包括电介质。

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