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1. 发明申请

WO2014070376A1 TUNING FOR DISTRIBUTED DATA STORAGE AND PROCESSING SYSTEMS 审中-公开
标题翻译：调谐分布式数据存储和处理系统
公开(公告)号：WO2014070376A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/063476
申请日：2013-10-04
申请人： INTEL CORPORATION , LIAO, Guangdeng, D. , YIGITBASI, Nezih , WILLKE, Theodore , DATTA, Kushal
发明人： LIAO, Guangdeng, D. , YIGITBASI, Nezih , WILLKE, Theodore , DATTA, Kushal
IPC分类号： G06F17/00 , G06F17/30
CPC分类号： G06F17/30306 , G06F9/5027 , G06F2209/501 , G06F2209/5018
摘要： The present disclosure describes tuning for distributed data and storage and processing systems. A device may comprise a tuner module configured to determine a distributed data and storage and processing system configuration based at least on configuration information available in the device, and to adjust the distributed data and storage and processing system configuration based on a baseline configuration. The tuner module may be further configured to then determine sample information for the distributed data and storage and processing systems derived from actual distributed data and storage and processing system operation, and to use the sample information in creating a performance model of the distributed data and storage and processing system. The tuner module may be further configured to then evaluate configuration changes to the system based on the performance model, and to determine a recommended distributed data and storage and processing system configuration based on the evaluation.
摘要翻译：本公开描述了对分布式数据和存储和处理系统的调整。设备可以包括调谐器模块，其被配置为基于至少基于设备中可用的配置信息来确定分布式数据和存储和处理系统配置，并且基于基线配置来调整分布式数据和存储和处理系统配置。调谐器模块还可以被配置为随后确定从实际分布式数据和存储和处理系统操作导出的分布式数据和存储和处理系统的样本信息，并且使用样本信息来创建分布式数据和存储器的性能模型和处理系统。调谐器模块还可以被配置为随后基于性能模型评估对系统的配置改变，并且基于评估来确定推荐的分布式数据和存储和处理系统配置。

2. 发明申请

WO2012102989A3 CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY 审中-公开
公开(公告)号：WO2012102989A3
公开(公告)日：2012-08-02
申请号：PCT/US2012/022170
申请日：2012-01-23
申请人： INTEL CORPORATION , FANG, Zhen , ZHAO, Li , IYER, Ravishankar , MAKINENI, Srihari , LIAO, Guangdeng
发明人： FANG, Zhen , ZHAO, Li , IYER, Ravishankar , MAKINENI, Srihari , LIAO, Guangdeng
IPC分类号： G06F1/00 , G06F13/14 , G06F12/00
摘要： An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.

3. 发明申请

WO2012102989A2 CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY 审中-公开
标题翻译：电路选择，至少一部分，至少一个记忆
公开(公告)号：WO2012102989A2
公开(公告)日：2012-08-02
申请号：PCT/US2012022170
申请日：2012-01-23
申请人： INTEL CORP , FANG ZHEN , ZHAO LI , IYER RAVISHANKAR , MAKINENI SRIHARI , LIAO GUANGDENG
发明人： FANG ZHEN , ZHAO LI , IYER RAVISHANKAR , MAKINENI SRIHARI , LIAO GUANGDENG
IPC分类号： G06F1/00 , G06F12/00 , G06F13/14
CPC分类号： G06F12/0813 , Y02D10/13
摘要： An embodiment may include circuitry to select, at least in part, from a plurality of memories, at least one memory to store data. The memories may be associated with respective processor cores. The circuitry may select, at least in part, the at least one memory based at least in part upon whether the data is included in at least one page that spans multiple memory lines that is to be processed by at least one of the processor cores. If the data is included in the at least one page, the circuitry may select, at least in part, the at least one memory, such that the at least one memory is proximate to the at least one of the processor cores. Many alternatives, variations, and modifications are possible.
摘要翻译：一个实施例可以包括至少部分地从多个存储器中选择至少一个存储器来存储数据的电路。存储器可以与相应的处理器核心相关联。该电路至少部分地至少部分地选择至少一个存储器，该至少一个存储器至少部分地基于是否将数据包括在跨越由至少一个处理器核处理的多个存储器线的至少一个页面中。如果数据被包括在至少一个页面中，则电路可以至少部分地选择至少一个存储器，使得至少一个存储器靠近该至少一个处理器核心。许多替代方案，变化和修改是可能的。

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