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1. 发明申请

WO2012050267A1 DIGITAL RE-SAMPLING APPARATUS USING FRACTIONAL DELAY GENERATOR 审中-公开
标题翻译：数字再采样器采用分时延迟发生器
公开(公告)号：WO2012050267A1
公开(公告)日：2012-04-19
申请号：PCT/KR2010/009582
申请日：2010-12-30
申请人： INNOWIRELESS CO., LTD. , JOUNG, Jinsoup , HA, Kyeongmin , LEE, Joohyeong
发明人： JOUNG, Jinsoup , HA, Kyeongmin , LEE, Joohyeong
IPC分类号： H03H17/02 , H03H17/00
CPC分类号： H03H17/0444 , H03H17/0027 , H03H17/0642
摘要： Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table.
摘要翻译：本文公开了一种数字再采样装置。数字重采样装置包括采样缓冲器，采样缓冲器控制单元，滤波器组，第一延迟组，分数延迟常数表，组合器组和第二延迟组。采样缓冲器与输入采样频率同步地临时存储输入采样。采样缓冲器控制单元控制写入和读取操作。滤波器组包括等于级数的多个数字滤波器，并对输入样本进行滤波。第一个延迟组差分地延迟滤波器输出值。分数延迟常数表存储关于重新采样时间的信息。组合器组包括多个加法器和乘法器，执行操作，并且输出重新采样的值。第二延迟组引起延迟，使得每个组合器的输出可以与分数延迟常数表的每个输出同步。

2. 发明申请

WO2013115429A1 APPARATUS AND METHOD FOR GENERATING INTERLEAVER INDEX 审中-公开
标题翻译：用于生成交换索引的装置和方法
公开(公告)号：WO2013115429A1
公开(公告)日：2013-08-08
申请号：PCT/KR2012/001441
申请日：2012-02-24
申请人： INNOWIRELESS CO., LTD. , JOUNG, Jinsoup , LEE, Joohyeong , LIM, Jongho , KIM, Jaehwan
发明人： JOUNG, Jinsoup , LEE, Joohyeong , LIM, Jongho , KIM, Jaehwan
IPC分类号： H03M13/27
CPC分类号： H03M13/2771 , H03M13/2739 , H03M13/276 , H03M13/395 , H03M13/6561
摘要： Disclosed is an apparatus and a method for generating an internal interleaver index of a turbo encoder in parallel. There are effects of reducing the time spent for generating total indexes by generating indexes for a plurality of bits in parallel and improving the resource efficiency and the performance in the hardware implementation by calculating indexes for following bits through the use of an index calculated for a predetermined bit without the use of a multiplier and a divider.
摘要翻译：公开了并行地生成turbo编码器的内部交织器索引的装置和方法。通过使用针对预定的方式计算的索引来计算跟踪比特的索引，具有减少用于并行生成多个比特的索引并且提高资源效率和硬件实现中的性能来生成总索引的时间的效果位而不使用乘法器和分频器。

3. 发明申请

WO2013108952A1 TURBO ENCODER APPARATUS 审中-公开
标题翻译：涡轮编码器设备
公开(公告)号：WO2013108952A1
公开(公告)日：2013-07-25
申请号：PCT/KR2012/001439
申请日：2012-02-24
申请人： INNOWIRELESS CO., LTD. , JOUNG, Jinsoup , LEE, Joohyeong , LIM, Jongho , YOOK, Seungkeun , SHIN, Ji Hye
发明人： JOUNG, Jinsoup , LEE, Joohyeong , LIM, Jongho , YOOK, Seungkeun , SHIN, Ji Hye
IPC分类号： H03M13/00
CPC分类号： H03M13/47 , H03M13/235 , H03M13/2903 , H03M13/2957 , H03M13/2993 , H03M13/6525 , H03M13/6575
摘要： Disclosed is a turbo encoder apparatus using an improved signal processing method in order to enhance a speed of a turbo encoder used in a channel coding technology. There are effects of reducing a time spent for performing an encoding by performing the encoding in the unit of plural bits every clock cycle and performing a turbo encoding with a structure optimized for a total signal processing processor through the assembly of input forms of encoding output bitstreams in a subsequent signal processing step for encoding through the bitstream assembling apparatus.
摘要翻译：公开了一种使用改进的信号处理方法的turbo编码器装置，以便提高在信道编码技术中使用的turbo编码器的速度。通过以每个时钟周期的多个比特为单位执行编码，并且通过编码输出比特流的输入形式的组合来执行利用针对总信号处理处理器优化的结构的turbo编码来减少执行编码所花费的时间的效果在随后的信号处理步骤中，通过比特流组合装置进行编码。

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