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    • 1. 发明申请
    • LOW-VOLTAGE CMOS SPACE-EFFICIENT 15 KV ESD PROTECTION FOR COMMON-MODE HIGH-VOLTAGE RECEIVERS
    • 低电压CMOS共模高压接收器的CMOS空间有效15 KV ESD保护
    • WO2009131997A3
    • 2010-01-07
    • PCT/US2009041246
    • 2009-04-21
    • EXAR CORPFARZAN BAHMANLE HUNG PHAM
    • FARZAN BAHMANLE HUNG PHAM
    • H02H9/00
    • H01L27/0255
    • An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs.
    • 静电放电保护装置设置在差分信号对的真正补码输入引脚和接地节点之间。 一个公共节点将三个二极管堆叠在一起。 第一和第二二极管堆叠各自连接到差分信号对输入引脚之一。 第三个二极管堆叠耦合到接地节点。 每个二极管堆叠由低浓度n-阱区域内的一对高浓度p型接触掺杂区制造。 p型接触掺杂剂区域中的每一个被配置为形成与阴极串联连接的背对背二极管。 在保护共模接收器时,来自ESD事件的电流被引导到地而不是互补接收器节点。 与完全并行配置的差分信号对相比,二极管堆叠能够承受15 kV的入射,并可节省高达25%的面积。
    • 2. 发明申请
    • LOW-VOLTAGE CMOS SPACE-EFFICIENT 15 KV ESD PROTECTION FOR COMMON-MODE HIGH-VOLTAGE RECEIVERS
    • 低电压CMOS共模高压接收器的CMOS空间有效15 KV ESD保护
    • WO2009131997A2
    • 2009-10-29
    • PCT/US2009/041246
    • 2009-04-21
    • EXAR CORPORATIONFARZAN, BahmanLE, Hung, Pham
    • FARZAN, BahmanLE, Hung, Pham
    • H02H9/00
    • H01L27/0255
    • An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs.
    • 静电放电保护装置设置在差分信号对的真正补码输入引脚和接地节点之间。 一个公共节点将三个二极管堆叠在一起。 第一和第二二极管堆叠各自连接到差分信号对输入引脚之一。 第三个二极管堆叠耦合到接地节点。 每个二极管堆叠由低浓度n-阱区域内的一对高浓度p型接触掺杂区制造。 p型接触掺杂剂区域中的每一个被配置为形成与阴极串联连接的背对背二极管。 在保护共模接收器时,来自ESD事件的电流被引导到地而不是互补接收器节点。 与完全并行配置的差分信号对相比,二极管堆叠能够承受15 kV的入射,并可节省高达25%的面积。