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1. 发明申请

WO2012119108A2 SET-POINT RESOLUTION IMPROVEMENT FOR SWITCH MODE POWER SUPPLIES 审中-公开
标题翻译：开关模式电源的设定点分辨率改进
公开(公告)号：WO2012119108A2
公开(公告)日：2012-09-07
申请号：PCT/US2012027563
申请日：2012-03-02
申请人： EXAR CORP , BROWN LAWRENCE , WEINSTEIN JASON , ZHAO ZHENYU , HU ZONGGI JOHNNY
发明人： BROWN LAWRENCE , WEINSTEIN JASON , ZHAO ZHENYU , HU ZONGGI JOHNNY
IPC分类号： H03M1/20 , H04N19/89
CPC分类号： H02M1/36 , H02M2001/0012 , H02M2001/0025
摘要： A Digital-to-Analog Converter (DAC) produces an analog reference value from a first reference input. The analog reference value and an output value are used to produce an analog error signal. An Analog-to-Digital Converter (ADC) converts the analog error signal to a digital value. The ADC has higher level of resolution than the DAC. An error encoder adjusts the digital value to produce a digital error value using a second reference input.
摘要翻译：数模转换器（DAC）从第一参考输入产生模拟参考值。模拟参考值和输出值用于产生模拟误差信号。模数转换器（ADC）将模拟误差信号转换为数字值。 ADC的分辨率高于DAC。错误编码器使用第二个参考输入来调整数字值以产生数字误差值。

2. 发明申请

WO2009114474A3 COMBINATION OFFSET VOLTAGE AND BIAS CURRENT AUTO-ZERO CIRCUIT 审中-公开
标题翻译：组合偏置电压和偏置电流自动调零电路
公开(公告)号：WO2009114474A3
公开(公告)日：2010-01-07
申请号：PCT/US2009036544
申请日：2009-03-09
申请人： EXAR CORP , RANDLETT RICHARD W
发明人： RANDLETT RICHARD W
IPC分类号： H03F1/02
CPC分类号： H03F3/087 , H03F3/45475 , H03F2203/45136 , H03F2203/45528 , H03F2203/45534 , H03F2203/45616
摘要： A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.
摘要翻译：具有输入采集环路和输出采集环路的电路用于补偿运算放大器的输入失调电压和偏置电流误差。

3. 发明申请

WO2008106456A3 UNIVERSAL AND FAULT-TOLERANT MULTIPHASE DIGITAL PWM CONTROLLER FOR HIGH-FREQUENCY DC-DC CONVERTERS 审中-公开
标题翻译：用于高频DC-DC转换器的通用和容错多用数字PWM控制器
公开(公告)号：WO2008106456A3
公开(公告)日：2010-01-07
申请号：PCT/US2008055028
申请日：2008-02-26
申请人： EXAR CORP , PRODIC ALEKSANDAR , LUKIC ZDRAVKO
发明人： PRODIC ALEKSANDAR , LUKIC ZDRAVKO
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.
摘要翻译：多相混合数字脉冲宽度调制器可以包括可在至少两个不同数量的状态之间选择以指示切换周期的第一部分的计数器。非时钟逻辑可以指示切换周期的第二部分。非锁定逻辑可以包括延迟线。

4. 发明申请

WO2009135039A2 INTERRUPT BASED MULTIPLEXED CURRENT LIMIT CIRCUIT 审中-公开
标题翻译：基于中断的多路电流限制电路
公开(公告)号：WO2009135039A2
公开(公告)日：2009-11-05
申请号：PCT/US2009042369
申请日：2009-04-30
申请人： EXAR CORP , GODER DIMITRY , HU ZONGQI , NGUYEN KENDRA
发明人： GODER DIMITRY , HU ZONGQI , NGUYEN KENDRA
IPC分类号： H03M1/12
CPC分类号： H02M3/157 , H02M3/1584 , H02M2001/0009
摘要： A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.
摘要翻译：开关电压调节器部分地包括N个输出级，环路ADC，多路复用器，电流ADC和中断块。环路模数转换器接收N个输出电压，每个N个输出电压与N个通道中的一个相关联。环路ADC适于改变每个施加到产生N个输出电压的N个输出级中的一个的N个信号的占空比。如果在至少两个采样时间期间在输出级感测的电压之间的差超过预定义的阈值，则中断块适于使多路复用器将输出级耦合到当前ADC。如果在输出级感测的电压与参考电压之间的差超过预定义的阈值，则中断块还可以适于使多路复用器将输出级耦合到当前ADC模块。

5. 发明申请

WO2006093616A3 NETWORK ADDRESS FILTER INCLUDING RANDOM ACCESS MEMORY 审中-公开
标题翻译：网络地址过滤器，包括随机存取存储器
公开(公告)号：WO2006093616A3
公开(公告)日：2007-11-01
申请号：PCT/US2006003773
申请日：2006-02-03
申请人： EXAR CORP , RAO RAMANA , HOMER RUSSELL , KRALL DONALD
发明人： RAO RAMANA , HOMER RUSSELL , KRALL DONALD
IPC分类号： H04L12/28
CPC分类号： H04L12/437 , H04L12/18 , H04L45/7453
摘要： A network address filter that includes a random access memory configured to store network address data, a processor, and a comparator. The processor is configured to execute a hash function on input data to obtain a random access memory address that is applied to the random access memory to obtain network address data from the random access memory address. The comparator is configured to compare the input data to the network address data and indicate a match between the input data and the network address data.
摘要翻译：一种网络地址过滤器，包括被配置为存储网络地址数据的随机存取存储器，处理器和比较器。处理器被配置为对输入数据执行散列函数以获得应用于随机存取存储器的随机存取存储器地址，以从随机存取存储器地址获得网络地址数据。比较器被配置为将输入数据与网络地址数据进行比较，并指示输入数据和网络地址数据之间的匹配。

6. 发明申请

WO2012030483A2 DEJITTER (DESYNCHRONIZE) TECHNIQUE TO SMOOTH GAPPED CLOCK WITH JITTER/WANDER ATTENUATION USING ALL DIGITAL LOGIC 审中-公开
标题翻译： DEJITTER（DESYNCHRONIZE）技术使用所有数字逻辑使用抖动/漫反射衰减平滑时钟
公开(公告)号：WO2012030483A2
公开(公告)日：2012-03-08
申请号：PCT/US2011046962
申请日：2011-08-08
申请人： EXAR CORP , LAWANGE OMESHWAR SURYAKANT
发明人： LAWANGE OMESHWAR SURYAKANT
IPC分类号： H04L7/00
CPC分类号： H04J3/076
摘要： Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.
摘要翻译：数字逻辑接收具有指定频率和频率偏移的指定频率和频率偏移的有间隙和抖动的时钟信号，以及具有低抖动的规范允许的具有相同指定频率和不同频率偏移的参考时钟信号。数字逻辑在延长的时间周期内增加和/或去除参考时钟信号的周期，以产生具有接近缺口和抖动时钟信号的频率的低抖动的产生的时钟信号。所产生的时钟信号作为反馈被提供给数字频率比较器，并且还作为具有50％占空比的最终去抖平滑时钟输出。

7. 发明申请

WO2009131997A3 LOW-VOLTAGE CMOS SPACE-EFFICIENT 15 KV ESD PROTECTION FOR COMMON-MODE HIGH-VOLTAGE RECEIVERS 审中-公开
标题翻译：低电压CMOS共模高压接收器的CMOS空间有效15 KV ESD保护
公开(公告)号：WO2009131997A3
公开(公告)日：2010-01-07
申请号：PCT/US2009041246
申请日：2009-04-21
申请人： EXAR CORP , FARZAN BAHMAN , LE HUNG PHAM
发明人： FARZAN BAHMAN , LE HUNG PHAM
IPC分类号： H02H9/00
CPC分类号： H01L27/0255
摘要： An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs.
摘要翻译：静电放电保护装置设置在差分信号对的真正补码输入引脚和接地节点之间。一个公共节点将三个二极管堆叠在一起。第一和第二二极管堆叠各自连接到差分信号对输入引脚之一。第三个二极管堆叠耦合到接地节点。每个二极管堆叠由低浓度n-阱区域内的一对高浓度p型接触掺杂区制造。 p型接触掺杂剂区域中的每一个被配置为形成与阴极串联连接的背对背二极管。在保护共模接收器时，来自ESD事件的电流被引导到地而不是互补接收器节点。与完全并行配置的差分信号对相比，二极管堆叠能够承受15 kV的入射，并可节省高达25％的面积。

8. 发明申请

WO2008109601A3 APPARATUS AND METHODS FOR IMPROVING THE TRANSIENT RESPONSE CAPABILITY OF A SWITCHING POWER SUPPLY 审中-公开
标题翻译：改善开关电源瞬态响应能力的装置和方法
公开(公告)号：WO2008109601A3
公开(公告)日：2009-12-30
申请号：PCT/US2008055800
申请日：2008-03-04
申请人： EXAR CORP , KERNAHAN KENT , SPANOCHE SORIN ANDREI , CHEN JINGQUAN
发明人： KERNAHAN KENT , SPANOCHE SORIN ANDREI , CHEN JINGQUAN
IPC分类号： H02M3/335
CPC分类号： H02M3/1588 , H02M1/15 , H02M3/157 , Y02B70/1466
摘要： The transient response of a switching power supply is improved by providing one or more supplemental power sources connected to the output terminal of the power supply. In one embodiment additional current is provided when a sudden increase in load current causes a corresponding decrease in output voltage. In one embodiment current is discharged when a sudden decrease in load current causes a corresponding increase in output voltage. The supplemental power sources provide a fixed current for a fixed duration. In one embodiment the current provided from the power sources is variable according to the increase or decrease in load current. In some embodiments the supplemental current is provided for a time period approximating the time required for the switching power converter coil current to equal the new load current.
摘要翻译：通过提供连接到电源的输出端子的一个或多个补充电源来改善开关电源的瞬态响应。在一个实施例中，当负载电流的突然增加导致输出电压的相应降低时，提供额外的电流。在一个实施例中，当负载电流的突然降低导致输出电压的相应增加时，电流被放电。补充电源为固定持续时间提供固定电流。在一个实施例中，从电源提供的电流可根据负载电流的增加或减小而变化。在一些实施例中，补充电流被设置为接近开关功率转换器线圈电流所需时间等于新的负载电流的时间段。

9. 发明申请

WO2008100970A3 METHOD FOR CHARGING A BATTERY USING A CONSTANT CURRENT ADAPTED TO PROVIDE A CONSTANT RATE OF CHANGE OF OPEN CIRCUIT BATTERY VOLTAGE 审中-公开
标题翻译：使用适应于恒定电流的电池充电以提供持续的开路电流变化率的方法电池电压
公开(公告)号：WO2008100970A3
公开(公告)日：2009-01-22
申请号：PCT/US2008053768
申请日：2008-02-12
申请人： EXAR CORP , KERNAHAN KENT , RIBEIRO MILTON D , ZHOU DONGSHENG , KLEIN LARRY A
发明人： KERNAHAN KENT , RIBEIRO MILTON D , ZHOU DONGSHENG , KLEIN LARRY A
IPC分类号： H02J7/16
CPC分类号： H02J7/045 , H01M10/44 , H01M10/48 , H02J7/0077
摘要： A constant battery charging current is periodically adjusted as needed such that the change in battery voltage increases approximately linearly during the charging period. Charging may be performed in three phases. A first phase charges with a low current until the battery voltages rises to a certain minimum. During a second phase a constant current is provided and periodically increased if the rate of change of battery voltage is less than a predetermined value. A third phase begins when the battery voltage attains a predetermined value, wherein a constant voltage is applied to the battery while the battery current draw is periodically monitored. Charging is stopped when the battery current draw falls to a predetermined value or when the charging current drops to a value that is a certain percentage of the charging current at the termination of phase two.
摘要翻译：根据需要周期性地调节恒定的电池充电电流，使得电池电压的变化在充电期间近似线性地增加。充电可以分三个阶段进行。第一阶段以低电流充电直到电池电压上升到一定的最小值。在第二阶段期间，如果电池电压的变化率小于预定值，则提供恒定电流并且周期性地增加。当电池电压达到预定值时，第三阶段开始，其中在电池电流消耗被周期性地监视的同时向电池施加恒定电压。当电池电流消耗下降到预定值时或当充电电流下降到在阶段2结束时充电电流的一定百分比的值时，停止充电。

10. 发明申请

WO2007106645A3 ELIMINATION OF DUMMY DETECTOR ON OPTICAL DETECTORS USING INPUT COMMON MODE FEEDBACK 审中-公开
标题翻译：使用输入公共模式反馈消除光学检测器上的检测器
公开(公告)号：WO2007106645A3
公开(公告)日：2008-11-20
申请号：PCT/US2007062431
申请日：2007-02-20
申请人： EXAR CORP , RANDLETT RICHARD W
发明人： RANDLETT RICHARD W
IPC分类号： H03F3/08
CPC分类号： H03F3/087 , H03F1/08 , H03F3/45475 , H03F3/45928 , H03F3/45941 , H03F2203/45061 , H03F2203/45078 , H03F2203/45424 , H03F2203/45561
摘要： A voltage reference forces a constant voltage at the inputs to an amplifier, thereby negating a need for a dummy detector on the non-active input of the amplifier.
摘要翻译：电压基准在放大器的输入端施加恒定电压，从而不需要在放大器的非有效输入端上的虚拟检测器。

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