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1. 发明申请

WO1995035548A1 ANALOG MULTIPLIER 审中-公开
标题翻译：模拟乘法器
公开(公告)号：WO1995035548A1
公开(公告)日：1995-12-28
申请号：PCT/AU1995000360
申请日：1995-06-20
申请人： UNISEARCH LIMITED , KWOK, Chee, Yee , MEHRVARZ, Hamid, Reza
发明人： UNISEARCH LIMITED
IPC分类号： G06G07/16
CPC分类号： H03D7/1441 , G06G7/164 , H03D7/1458 , H03D7/1491 , H03D2200/0007 , H03D2200/0043
摘要： A four-quadrant multiplier using multiple input floating-gate MOS transistors is provided. It is based on the square law characteristics of the MOS transistor and can be realised with only four floating gate MOS transistors, two resistors and a current source. The four floating gate transistors are configured with their sources connected in common and biased by a single current source. Output is taken between two common drain connections. Each transistor has three control gates with two being provided for selected ones of the two input signals and one for a biasing signal (optional). Input signals can be connected to the control gates in either a differential or single ended configuration. In one application, a programmable synaptic cell for neural networks employs the multi-input floating-gate MOS four-quadrant analog multiplier. Varying of the neural weight connection strength of each synaptic cell is achieved by two possible methods. One method involves programming charges into or out of the primary floating-gate of the MFMOS devices associated with the multiplier. The other method is to configure the third input gate of each MFMOS device of the multiplier as another (secondary) floating-gate structure whereby charge can be programmed into or out of this secondary floating-gate structure, and its coupling area to the primary floating-gate would determine the neural weight. The differential output current is proportional to the product of the input signal and the programmed charge difference. In a natural extension, an array of individually programmable synaptic cells form a neural network.
摘要翻译：提供了使用多输入浮栅MOS晶体管的四象限乘法器。它是基于MOS晶体管的平方律特性，只能用四个浮栅MOS晶体管，两个电阻和一个电流源实现。四个浮栅晶体管配置成其源极共同连接并由单个电流源偏置。输出在两个通用的漏极连接之间。每个晶体管具有三个控制栅极，其中两个输入信号中选定的一个控制栅极被提供，一个用于偏置信号（可选）。输入信号可以以差分或单端配置连接到控制门。在一个应用中，用于神经网络的可编程突触单元采用多输入浮栅MOS四象限模拟乘法器。通过两种可能的方法来实现每个突触细胞的神经重量连接强度的变化。一种方法涉及将费用编程到与乘法器相关联的MFMOS设备的主浮动栅极中或从外部进行。另一种方法是将乘法器的每个MFMOS器件的第三输入栅极配置为另一（次级）浮栅结构，由此可以将电荷编程到或从该次级浮栅结构中进行编程，并将其耦合区域与主浮置门将确定神经重量。差分输出电流与输入信号与编程的电荷差的乘积成比例。在自然延伸中，单独编程的突触细胞阵列形成神经网络。

2. 发明申请

WO2016201526A1 SILICON FILM AND PROCESS FOR FORMING SILICON FILM 审中-公开
标题翻译：硅胶膜及其制备方法
公开(公告)号：WO2016201526A1
公开(公告)日：2016-12-22
申请号：PCT/AU2016/050520
申请日：2016-06-20
申请人： KWOK, Chee Yee , MICHAEL, Aron
发明人： KWOK, Chee Yee , MICHAEL, Aron
IPC分类号： C23C14/30 , C23C14/00 , C23C14/14 , C23C14/16 , C23C14/24 , H01L27/00 , H01L27/20 , H01L21/00 , H01L21/62 , H01L21/70 , H01L21/77 , H01L41/00 , H01L41/02 , H01L41/04 , H01L41/08 , H01L41/18 , H01L41/35
CPC分类号： H01L21/02631 , C23C14/14 , C23C14/30 , H01L21/02532 , H01L21/02595 , H01L21/02609 , H01L21/62 , H01L41/081 , H01L41/314
摘要： A process for forming a thick silicon film comprises depositing a thick film of silicon by ultra-high vacuum electron beam deposition.
摘要翻译：用于形成厚硅膜的方法包括通过超高真空电子束沉积沉积厚的硅膜。

3. 发明申请

WO2012003530A9 OPTICAL BUS IN 3D INTEGRATED CIRCUIT STACK 审中-公开
标题翻译： 3D集成电路堆叠中的光学总线
公开(公告)号：WO2012003530A9
公开(公告)日：2012-03-08
申请号：PCT/AU2011000838
申请日：2011-07-04
申请人： NEWSOUTH INNOVATIONS PTY LTD , KWOK CHEE YEE , MICHAEL ARON , XU YIWEI
发明人： KWOK CHEE YEE , MICHAEL ARON , XU YIWEI
IPC分类号： G02B6/12 , G02B5/08 , G02B6/122 , G02B6/13 , H01L23/00
CPC分类号： H01L25/0657 , G02B6/12 , G02B6/12002 , G02B6/12004 , G02B6/4201 , G02B6/4204 , G02B6/43 , G02B2006/12104 , H01L21/302 , H01L23/544 , H01L24/70 , H01L2223/54426 , H01L2225/06527 , H01L2225/06534 , H01L2924/0002 , H01L2924/01014 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： An optical bus (130) of an integrated circuit (100) comprises: a polymer waveguide (112), a micromirror (114, 116), and an optical coupler (120). The polymer waveguide (112) is disposed in a via (110) formed through at least one die layer (102, 104, 106) of the integrated circuit (100) comprising an active circuit (210). The micromirror (114) is disposed adjacent to the via (110) and optically coupled to the polymer waveguide (112). The optical coupler (120) is connected to the polymer waveguide ( 112) to couple the active circuit (210) to the optical bus (130). A stacked integrated circuit (100) is described comprising such an optical bus (130). A method (800) of fabricating a rear 45° micromirror on a silicon substrate that can be used in the optical bus (130) is also described. Furthermore, alignment/lock mechanisms for use in a stacked integrated circuit comprising first and second silicon substrates are described.
摘要翻译：集成电路（100）的光学总线（130）包括：聚合物波导（112），微镜（114,116）和光耦合器（120）。聚合物波导（112）设置在通过包括有源电路（210）的集成电路（100）的至少一个管芯层（102,104,106）形成的通孔（110）中。微镜（114）邻近通孔（110）设置并且光耦合到聚合物波导（112）。光耦合器（120）连接到聚合物波导（112）以将有源电路（210）耦合到光学总线（130）。描述了包括这种光学总线（130）的堆叠集成电路（100）。还描述了可以在光学总线（130）中使用的在硅衬底上制造后部45°微镜的方法（800）。此外，描述了用于包括第一和第二硅衬底的堆叠集成电路中的对准/锁定机构。

4. 发明申请

WO2012003530A1 OPTICAL BUS IN 3D INTEGRATED CIRCUIT STACK 审中-公开
标题翻译：三维集成电路堆栈中的光学总线
公开(公告)号：WO2012003530A1
公开(公告)日：2012-01-12
申请号：PCT/AU2011/000838
申请日：2011-07-04
申请人： NEWSOUTH INNOVATIONS PTY LIMITED , KWOK, Chee Yee , MICHAEL, Aron , XU, Yiwei
发明人： KWOK, Chee Yee , MICHAEL, Aron , XU, Yiwei
IPC分类号： G02B6/12 , G02B6/122 , H01L23/00 , G02B5/08 , G02B6/13
CPC分类号： H01L25/0657 , G02B6/12 , G02B6/12002 , G02B6/12004 , G02B6/4201 , G02B6/4204 , G02B6/43 , G02B2006/12104 , H01L21/302 , H01L23/544 , H01L24/70 , H01L2223/54426 , H01L2225/06527 , H01L2225/06534 , H01L2924/0002 , H01L2924/01014 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： An optical bus (130) of an integrated circuit (100) comprises: a polymer waveguide (112), a micromirror (114, 116), and an optical coupler (120). The polymer waveguide (112) is disposed in a via (110) formed through at least one die layer (102, 104, 106) of the integrated circuit (100) comprising an active circuit (210). The micromirror (114) is disposed adjacent to the via (110) and optically coupled to the polymer waveguide (112). The optical coupler (120) is connected to the polymer waveguide ( 112) to couple the active circuit (210) to the optical bus (130). A stacked integrated circuit (100) is described comprising such an optical bus (130). A method (800) of fabricating a rear 45° micromirror on a silicon substrate that can be used in the optical bus (130) is also described. Furthermore, alignment/lock mechanisms for use in a stacked integrated circuit comprising first and second silicon substrates are described.
摘要翻译：集成电路（100）的光总线（130）包括：聚合物波导（112），微镜（114,116）和光耦合器（120）。聚合物波导（112）设置在通过包括有源电路（210）的集成电路（100）的至少一个管芯层（102,104,106）形成的通孔（110）中。微镜（114）与通孔（110）相邻设置并光学耦合到聚合物波导（112）。光耦合器（120）连接到聚合物波导（112）以将有源电路（210）耦合到光学总线（130）。描述了包括这种光学总线（130）的堆叠集成电路（100）。制造后部45°的方法（800）还描述了可以在光学总线（130）中使用的硅基板上的微镜。此外，描述了用于包括第一和第二硅衬底的堆叠集成电路中的对准/锁定机构。

5. 发明申请

WO2012003529A1 PIEZO-ELECTRIC BASED MICRO-ELECTRO-MECHANICAL LENS ACTUATION SYSTEM 审中-公开
标题翻译：基于电机的微机电镜头致动系统
公开(公告)号：WO2012003529A1
公开(公告)日：2012-01-12
申请号：PCT/AU2011/000837
申请日：2011-07-04
申请人： NEWSOUTH INNOVATIONS PTY LIMITED , MICHAEL, Aron , KWOK, Chee Yee
发明人： MICHAEL, Aron , KWOK, Chee Yee
IPC分类号： B81B3/00 , B81B5/00 , G02B26/08 , H01L41/083
CPC分类号： G02B13/0075 , G02B26/0858 , G02B26/0875 , H01L41/0906 , H01L41/0953 , H01L41/0986
摘要： Disclosed is a piezo-electrically actuated micro-mechanical deformable member comprising a corrugated longitudinal beam (521) formed in a substrate, and having a first anchored end (502) and a second end (509), as well as a plurality of piezoelectric film (PZET) actuating segments (522, 523, 524) formed in or on at least some grooves and ridges of the corrugated beam, the beam (521) being configured to assume one of a number of different geometric configurations depending upon which of a corresponding set of electric actuation signals (105) are applied to the PZET elements, the electric actuation signals establishing corresponding electric fields in the associated PZET segments to thereby deform the member.
摘要翻译：公开了一种压电电致动的微机械可变形构件，其包括形成在基板中的波纹纵向梁（521），并且具有第一锚定端（502）和第二端（509），以及多个压电膜（PZET）致动段（522,523,524），其形成在波纹梁的至少一些凹槽和脊中或之上，所述梁（521）被配置为根据哪个相应的一组电致动信号（105）被施加到PZET元件，电致动信号在相关联的PZET段中建立相应的电场，从而使构件变形。

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