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1. 发明申请

WO2017083751A1 SERIAL DEVICE EMULATOR USING TWO MEMORY LEVELS WITH DYNAMIC AND CONFIGURABLE RESPONSE 审中-公开
标题翻译：采用动态可配置响应的两个存储器电平的串行器件仿真器
公开(公告)号：WO2017083751A1
公开(公告)日：2017-05-18
申请号：PCT/US2016/061669
申请日：2016-11-11
申请人： TOTAL PHASE, INC. , HOLDEN, Thomas, P. , KUMARAN, Santhanam
发明人： HOLDEN, Thomas, P. , KUMARAN, Santhanam
IPC分类号： G06F13/00
CPC分类号： G06F9/455 , G06F9/4411 , G11C11/005 , G11C14/0009 , G11C14/0054
摘要： A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the SRAM the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response data in the SRAM, store in the DRAM additional response data, and store in the lookup table the memory location and size of the additional response data in the DRAM. The processor is configured to receive the command from a host device, retrieve the first response data from the registers or the SRAM, and send the first response data to the host. If the command includes additional response data, the processor is configured to concurrently retrieve the additional response data from DRAM and send the additional response data to the host.
摘要翻译：公开了一种数字逻辑器件，其包括寄存器，SRAM，DRAM和处理器，该处理器被配置成将第一响应数据的初始部分存储在寄存器中以将命令存储在SRAM中，响应数据。处理器进一步被配置为在SRAM中将第一响应数据的存储器位置和大小存储在查找表中，将附加响应数据存储在DRAM附加响应数据中，并将附加响应数据的存储器位置和大小存储在查找表中 DRAM。处理器被配置为从主机设备接收命令，从寄存器或SRAM检索第一响应数据，并将第一响应数据发送到主机。如果该命令包括额外的响应数据，则该处理器被配置成同时从DRAM检索额外的响应数据并将该额外的响应数据发送给主机。

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