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1. 发明申请

WO2011116116A3 LOGIC BUILT-IN SELF-TEST PROGRAMMABLE PATTERN BIT MASK 审中-公开
公开(公告)号：WO2011116116A3
公开(公告)日：2011-09-22
申请号：PCT/US2011/028699
申请日：2011-03-16
申请人： QUALCOMM INCORPORATED , KIM, Hong S. , POLICKE, Paul F. , BASSETT, Paul Douglas
发明人： KIM, Hong S. , POLICKE, Paul F. , BASSETT, Paul Douglas
IPC分类号： G06F11/27 , G01R31/3185
摘要： In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built in self test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.

2. 发明申请

WO2011116116A2 LOGIC BUILT-IN SELF-TEST PROGRAMMABLE PATTERN BIT MASK 审中-公开
标题翻译：逻辑内置自检模式可编程模式掩码
公开(公告)号：WO2011116116A2
公开(公告)日：2011-09-22
申请号：PCT/US2011028699
申请日：2011-03-16
申请人： QUALCOMM INC , KIM HONG S , POLICKE PAUL F , BASSETT PAUL DOUGLAS
发明人： KIM HONG S , POLICKE PAUL F , BASSETT PAUL DOUGLAS
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/318533 , G01R31/318555
摘要： In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built in self test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.
摘要翻译：在特定实施例中，公开了一种方法，其包括将多个扫描链内的故障比特位置映射到存储器掩码的存储器位置。该方法还包括使用存储器掩码在半导体器件上执行内置自检（LBIST）测试的逻辑，以选择性地掩蔽多个扫描链中的某些结果。结果与半导体器件上LBIST测试的性能相关。

3. 发明申请

WO2012065064A1 FEEDBACK SCAN ISOLATION AND SCAN BYPASS ARCHITECTURE 审中-公开
标题翻译：反馈扫描隔离和扫描旁路建筑
公开(公告)号：WO2012065064A1
公开(公告)日：2012-05-18
申请号：PCT/US2011/060372
申请日：2011-11-11
申请人： QUALCOMM INCORPORATED , POLICKE, Paul F. , KIM, Hong S. , BASSETT, Paul Douglas
发明人： POLICKE, Paul F. , KIM, Hong S. , BASSETT, Paul Douglas
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558 , G01R31/318572
摘要： A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.
摘要翻译：反馈扫描隔离和旁路架构设备和方法。该装置包括核心逻辑，以及输入和输出多路复用器。输入复用器基于测试信号选择性地向核心输入提供功能输入或核心输出。输出复用器基于测试信号选择性地将核心输出或输入多路复用器输出提供给功能输出。当测试信号指示核心反馈测试时，输出多路复用器输出核心输出，输入多路复用器将核心输出反馈到核心输入。当测试信号指示旁路测试时，输入多路复用器输出功能输入，输出多路复用器输出旁路核心逻辑的功能输入。当有时序问题时，逻辑可以阻止反馈或旁路信号。当功能输入和输出数量不同时，逻辑可以修改反馈或旁路信号的数量。

4. 发明申请

WO2012040378A1 DEBUGGER BASED MEMORY DUMP USING BUILT IN SELF TEST 审中-公开
标题翻译：使用内置自检功能进行基于调试器的存储器抽取
公开(公告)号：WO2012040378A1
公开(公告)日：2012-03-29
申请号：PCT/US2011/052632
申请日：2011-09-21
申请人： QUALCOMM INCORPORATED , KIM, Hong S. , POLICKE, Paul F. , BASSETT, Paul Douglas
发明人： KIM, Hong S. , POLICKE, Paul F. , BASSETT, Paul Douglas
IPC分类号： G06F11/36
CPC分类号： G06F11/3656
摘要： A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.
摘要翻译：一种用于执行存储器转储的方法和装置。该方法包括通过BIST包装器从调试器向存储器阵列提供存储器位置，以及通过从存储器阵列中的存储器位置读取的调试器接收数据。该方法可以包括从调试器发送转储使能信号，并且BIST包装器响应于转储使能信号而选择性地将存储器位置提供给存储器阵列。该方法可以包括将转储使能信号发送到耦合到BIST封装器中的寄存器的多路复用器，转储使能信号使多路复用器将存储器位置加载寄存器。该方法可以包括在从存储器位置读取数据之前异步发送写入禁止信号到存储器阵列。所接收的数据可以从从存储器位置读取的较大数据集中选择。

5. 发明申请

WO2011109487A8 METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE 审中-公开
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：WO2011109487A8
公开(公告)日：2011-10-27
申请号：PCT/US2011026826
申请日：2011-03-02
申请人： QUALCOMM INC , MOHAMMAD BAKER S , KIM HONG S , BASSETT PAUL DOUGLAS
发明人： MOHAMMAD BAKER S , KIM HONG S , BASSETT PAUL DOUGLAS
IPC分类号： G11C11/412 , G11C29/12 , G11C29/50
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal (138) at a controller (108) coupled to a semiconductor device (104). The method further includes biasing a well (142) of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit (106) that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译：在特定实施例中，一种方法包括在耦合到半导体器件（104）的控制器（108）处接收测试激活信号（138）。该方法还包括响应于所接收的测试激活信号偏置半导体器件的至少一个晶体管的阱（142）。该偏压由对控制器作出响应的偏置电路（106）提供。当井被偏置时，执行半导体器件的测试以产生测试数据。

6. 发明申请

WO2011109487A1 METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE 审中-公开
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：WO2011109487A1
公开(公告)日：2011-09-09
申请号：PCT/US2011/026826
申请日：2011-03-02
申请人： QUALCOMM Incorporated , MOHAMMAD, Baker S. , KIM, Hong S. , BASSETT, Paul Douglas
发明人： MOHAMMAD, Baker S. , KIM, Hong S. , BASSETT, Paul Douglas
IPC分类号： G11C11/412 , G11C29/12 , G11C29/50
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal (134) at a controller (108) coupled to a semiconductor device (104). The method further includes biasing a well (142) of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit (106) that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译：在特定实施例中，一种方法包括在耦合到半导体器件（104）的控制器（108）处接收测试激活信号（134）。该方法还包括响应于所接收的测试激活信号偏置半导体器件的至少一个晶体管的阱（142）。该偏压由对控制器作出响应的偏置电路（106）提供。当井被偏置时，执行半导体器件的测试以产生测试数据。

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