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1. 发明申请

WO2010015610A1 A METHOD, APPARATUS AND SOFTWARE FOR PROVIDING REDUNDANCY IN A SET OF STORAGE MODULES EACH COMPRISING A SET OF ONE OR MORE STORAGE ELEMENTS CONNECTED TO A STORAGE CONTROLLER BY CONNECTION MEANS 审中-公开
标题翻译：一种用于在存储模块中提供冗余的方法，装置和软件，每个存储模块包含通过连接方式连接到存储控制器的一组或多个存储元件
公开(公告)号：WO2010015610A1
公开(公告)日：2010-02-11
申请号：PCT/EP2009/060054
申请日：2009-08-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JUDD, Ian, David , RICKARD, Thomas, William
发明人： JUDD, Ian, David , RICKARD, Thomas, William
IPC分类号： G06F11/20
CPC分类号： G06F11/201 , G06F11/2092
摘要： A method, apparatus and software is disclosed for managing storage controller failure in a set of storage modules each comprising a set of one or more storage elements connected to a storage controller via connection means, in which at least one of the storage modules is provided with additional storage system fabric for providing a redundant connection to a storage controller of another storage module.
摘要翻译：公开了一种用于管理一组存储模块中的存储控制器故障的方法，装置和软件，每个存储模块包括经由连接装置连接到存储控制器的一个或多个存储元件的集合，其中至少一个存储模块具有附加存储系统结构，用于向另一个存储模块的存储控制器提供冗余连接。

2. 发明申请

WO2006084783A3 CONNECTION ERROR AVOIDANCE IN APPARATUS CONNECTED TO A POWER SUPPLY 审中-公开
标题翻译：连接到电源的设备中的连接错误避免
公开(公告)号：WO2006084783A3
公开(公告)日：2006-12-21
申请号：PCT/EP2006050286
申请日：2006-01-18
申请人： IBM , HYATT STEVE JOHN , JUDD IAN DAVID , NICHOLSON ROBERT BRUCE , QUELCH PAUL JONATHAN , RANDLE STEPHEN ARTHUR , SCALES WILLIAM JAMES
发明人： HYATT STEVE JOHN , JUDD IAN DAVID , NICHOLSON ROBERT BRUCE , QUELCH PAUL JONATHAN , RANDLE STEPHEN ARTHUR , SCALES WILLIAM JAMES
IPC分类号： G06F11/22
CPC分类号： G06F11/2289 , Y10T307/615
摘要： A logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, comprises: a pattern-generating component for generating an identifiable pattern for a patterned load to be drawn from a power supply connection; a load-drawing component, responsive to the pattern-generating component, 10 for drawing the patterned load from the power supply connection; and a testing component at the power consumer apparatus for testing across a signal connection for a responsive supply to satisfy demand for the patterned load by the power supply apparatus. The logic arrangement may further be embodied as a system or as a computer program.
摘要翻译：一种用于减少功率消耗装置和电源装置之间的连接中的误差的发生率的逻辑装置，包括：模式产生部件，用于产生用于从电源连接抽出的图案化负载的可识别图案; 响应于图案产生部件的负载绘图部件10，用于从电源连接中抽出图案化负载; 以及用于电力消费者装置的测试部件，用于通过用于响应电源的信号连接进行测试，以满足由电源装置对图案化负载的需求。逻辑布置还可以被体现为系统或计算机程序。

3. 发明申请

WO2005001841A2 SAFE WRITE TO MULTIPLY-REDUNDANT STORAGE 审中-公开
标题翻译：安全地写入冗余冗余存储
公开(公告)号：WO2005001841A2
公开(公告)日：2005-01-06
申请号：PCT/EP2004/051150
申请日：2004-06-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FAIRHURST, Matthew, John , JUDD, Ian, David , SCALES, William, James
发明人： FAIRHURST, Matthew, John , JUDD, Ian, David , SCALES, William, James
IPC分类号： G11C11/00
CPC分类号： G06F11/1076 , G06F2211/1009 , G11B20/1833
摘要： An arrangement of apparatus for safely writing data and parity to multiply-redundant storage comprises a first storage component operable to store at least a first mark in a storage device to index uniquely a pattern to be written by at least a data write; a write component operable to perform the at least data write; a further storage component operable to overwrite a mark in the storage device with at least a further mark to index uniquely a pattern to be written by a parity write; and a further write component operable to perform the parity write. Preferably, the first storage component comprises a second storage component operable to overwrite said at least first mark in said storage device with a second mark to index a pattern to be written by a first parity write; and the write component is further operable to perform the first parity write.
摘要翻译：用于将数据和奇偶校验安全地写入乘法冗余存储装置的装置的配置包括：第一存储组件，其可操作用于将至少第一标记存储在存储装置中以唯一地索引待写入的模式至少一个数据写入; 写入组件，可操作用于执行至少数据写入; 另一存储组件，其可操作以利用至少另一标记来重写存储装置中的标记以唯一地索引待通过奇偶写入写入的模式; 以及可操作来执行奇偶校验写入的另外的写入组件。优选地，所述第一存储组件包括第二存储组件，所述第二存储组件可操作以用第二标记覆盖所述存储设备中的所述至少第一标记以索引要通过第一奇偶校验写入写入的模式; 并且写入组件还可操作来执行第一次奇偶校验写入。

4. 发明申请

WO1992015054A1 DATA TRANSFER BETWEEN A DATA STORAGE SUBSYSTEM AND HOST SYSTEM 审中-公开
标题翻译：数据存储子系统和主机系统之间的数据传输
公开(公告)号：WO1992015054A1
公开(公告)日：1992-09-03
申请号：PCT/GB1991000256
申请日：1991-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JUDD, Ian, David , CATH, Roger, Goodwin , COCKBURN, Gordon, John , SHORT, William, Anthony , BUCKLAND, Patrick, Allen
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION
IPC分类号： G06F03/06
CPC分类号： G06F3/0601 , G06F2003/0692
摘要： Described is a technique for transferring data from a data storage system to a connected host data processing system. The subsystem comprises a device controller connected to one or more direct access storage devices e.g. disk drives. The system issues data transfer commands to the subsystem to iniciate transfer of data between system and device(s). Read/write data is transferred directly from device to host via a buffer in the controller. For a read operation, the read command specifies the data to be transferred and the start address in host memory to which it should be sent. The device controller is capable of amending the start address to which it actually sends the data. This provides a performance benefit for split data transfers. In addition, if an error occurs during a read operation, the controller can specify the host address to which the replacement data should be sent.
摘要翻译：描述了将数据从数据存储系统传送到连接的主机数据处理系统的技术。子系统包括连接到一个或多个直接访问存储设备的设备控制器，例如磁盘驱动器系统向子系统发出数据传输命令，以确定系统和设备之间的数据传输。读/写数据通过控制器中的缓冲区从设备直接传输到主机。对于读取操作，读取命令指定要发送的数据和主机存储器中的起始地址。设备控制器能够修改其实际发送数据的起始地址。这为分割数据传输提供了性能优势。另外，如果在读操作期间发生错误，则控制器可以指定应发送替换数据的主机地址。

5. 发明申请

WO2010097132A1 AN APPARATUS AND METHOD FOR EXPANDING A STORAGE CONTROLLER 审中-公开
标题翻译：一种用于扩展存储控制器的装置和方法
公开(公告)号：WO2010097132A1
公开(公告)日：2010-09-02
申请号：PCT/EP2009/067180
申请日：2009-12-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JUDD, Ian, David , SCALES, William, James , RICKARD, Thomas, William
发明人： JUDD, Ian, David , SCALES, William, James , RICKARD, Thomas, William
IPC分类号： G06F1/18
CPC分类号： G06F1/187
摘要： A modified electronics package and a method of manufacture of a modified electronics package with dimensions constrained by standards, comprising an envelope and a circuit structure. The circuit structure provides a free space within the dimensions, which contains a connector for connecting a further circuit structure with either the circuit structure or with a device outside the envelope. In further embodiments of the invention, the modified electronics package meets Storage Bridge Bay Working Group (SBB) specifications. It may also comprise a further circuit structure, which may be a PCIe adapter card or a data storage device. Further embodiments include an apparatus comprising a modified electronics package in combination with controller modules or further modified electronics packages, along with a rack mounted storage system with such apparatuses.
摘要翻译：一种改进的电子封装和制造具有由标准限制的尺寸的改进的电子封装的方法，包括封套和电路结构。电路结构提供了尺寸内的自由空间，其中包含用于将另外的电路结构与电路结构或外壳外部的装置连接的连接器。在本发明的另外的实施例中，改进的电子封装符合存储桥湾工作组（SBB）规范。它还可以包括另外的电路结构，其可以是PCIe适配器卡或数据存储设备。另外的实施例包括与控制器模块或进一步修改的电子封装组合的改进的电子封装以及具有这种装置的机架式存储系统的装置。

6. 发明申请

WO2006084783B1 CONNECTION ERROR AVOIDANCE IN APPARATUS CONNECTED TO A POWER SUPPLY 审中-公开
标题翻译：连接到电源的设备中的连接错误避免
公开(公告)号：WO2006084783B1
公开(公告)日：2007-02-22
申请号：PCT/EP2006050286
申请日：2006-01-18
申请人： IBM , HYATT STEVE JOHN , JUDD IAN DAVID , NICHOLSON ROBERT BRUCE , QUELCH PAUL JONATHAN , RANDLE STEPHEN ARTHUR , SCALES WILLIAM JAMES
发明人： HYATT STEVE JOHN , JUDD IAN DAVID , NICHOLSON ROBERT BRUCE , QUELCH PAUL JONATHAN , RANDLE STEPHEN ARTHUR , SCALES WILLIAM JAMES
IPC分类号： G06F11/22
CPC分类号： G06F11/2289 , Y10T307/615
摘要： A logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, comprises: a pattern-generating component for generating an identifiable pattern for a patterned load to be drawn from a power supply connection; a load-drawing component, responsive to the pattern-generating component, 10 for drawing the patterned load from the power supply connection; and a testing component at the power consumer apparatus for testing across a signal connection for a responsive supply to satisfy demand for the patterned load by the power supply apparatus. The logic arrangement may further be embodied as a system or as a computer program.
摘要翻译：一种用于减少功率消耗装置和电源装置之间的连接中的误差的发生率的逻辑装置，包括：图形产生部件，用于产生用于从电源连接中抽出的图案化负载的可识别图案; 响应于图案产生部件的负载拉伸部件10，用于从电源连接中抽出图案化负载; 以及用于电力消耗装置的测试部件，用于通过用于响应电源的信号连接进行测试，以满足由电源装置对图案化负载的需求。逻辑布置还可以体现为系统或计算机程序。

7. 发明申请

WO1992015058A1 DATA STORAGE SUBSYSTEM 审中-公开
标题翻译：数据存储子系统
公开(公告)号：WO1992015058A1
公开(公告)日：1992-09-03
申请号：PCT/GB1991000254
申请日：1991-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JUDD, Ian, David , SZATKOWSKI, Michael, Jan
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION
IPC分类号： G06F13/12
CPC分类号： G06F3/0601 , G06F13/124 , G06F2003/0692
摘要： A high performance data storage subsystem is described which is suitable for connection to a data processing system. The main functional units of the subsystem are (i) host adapter, (ii) device controller and (iii) direct access storage device (DASD). The functional units are interconnected by dedicated, point to point, full duplex serial links over which commands and data are trasmitted in the form of packets. The serial links also support packet multiplexing which allows commands transmitted over the serial link to be multiplexed with read or write data being transferred from and to the devices. A basic configuration of the subsystem comprises an adapter connected via a serial link to a controller which is in turn connected by four serial links to four DASDs. However the subsystem architecture described allows each adapter to be connected to up to four controllers, thus allowing a maximum of sixteen devices to be attached to one adapter.
摘要翻译：描述了适用于连接到数据处理系统的高性能数据存储子系统。子系统的主要功能单元是（i）主机适配器，（ii）设备控制器和（iii）直接存取存储设备（DASD）。功能单元通过专用的点对点全双工串行链路相互连接，命令和数据以数据包的形式传送到其上。串行链路还支持分组复用，允许通过串行链路发送的命令与从设备传送的读取或写入数据进行复用。子系统的基本配置包括通过串行链路连接到控制器的适配器，控制器又通过四个串行链路连接到四个DASD。然而，所描述的子系统架构允许每个适配器连接到最多四个控制器，从而允许最多16个设备连接到一个适配器。

8. 发明申请

WO2005001841A3 SAFE WRITE TO MULTIPLY-REDUNDANT STORAGE 审中-公开
标题翻译：安全写入多余的存储空间
公开(公告)号：WO2005001841A3
公开(公告)日：2005-09-09
申请号：PCT/EP2004051150
申请日：2004-06-17
申请人： IBM , FAIRHURST MATTHEW JOHN , JUDD IAN DAVID , SCALES WILLIAM JAMES
发明人： FAIRHURST MATTHEW JOHN , JUDD IAN DAVID , SCALES WILLIAM JAMES
IPC分类号： G06F3/06 , G06F11/10 , G11B20/18 , G11C11/00
CPC分类号： G06F11/1076 , G06F2211/1009 , G11B20/1833
摘要： An arrangement of apparatus for safely writing data and parity to multiply-redundant storage comprises a first storage component operable to store at least a first mark in a storage device to index uniquely a pattern to be written by at least a data write; a write component operable to perform the at least data write; a further storage component operable to overwrite a mark in the storage device with at least a further mark to index uniquely a pattern to be written by a parity write; and a further write component operable to perform the parity write. Preferably, the first storage component comprises a second storage component operable to overwrite said at least first mark in said storage device with a second mark to index a pattern to be written by a first parity write; and the write component is further operable to perform the first parity write.
摘要翻译：用于将数据和奇偶校验安全地写入多重冗余存储器的装置的布置包括：第一存储组件，可操作以将存储设备中的至少第一标记存储到唯一地通过至少数据写入要写入的模式; 写入组件，可操作以执行所述至少数据写入; 另外的存储组件可操作以用至少另外的标记覆盖存储设备中的标记，以唯一地索引要由奇偶校验写入写入的模式; 以及可操作以执行奇偶校验写入的另一写入组件。优选地，第一存储组件包括第二存储组件，可操作以用第二标记来覆盖所述存储设备中的所述至少第一标记，以对要由第一奇偶校验写入写入的模式进行索引; 并且写入组件进一步可操作以执行第一奇偶校验写入。

9. 发明申请

WO1992010894A1 SERIAL LINK DATA COMMUNICATION PROTOCOL 审中-公开
标题翻译：串行链路数据通信协议
公开(公告)号：WO1992010894A1
公开(公告)日：1992-06-25
申请号：PCT/GB1991000258
申请日：1991-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , SHAH, Vinay, Velji , JUDD, Ian, David , BEER, Reginald
发明人： INTERNATIONAL BUSINESS MACHINES CORPORATION
IPC分类号： H04L01/16
CPC分类号： H04L1/1803 , H04L1/1607 , H04L1/1835 , H04L1/1874 , H04L1/1887 , H04L29/06 , H04L69/28 , H04L69/324
摘要： Described is a system and method of communicating between first and second nodes connected by a serial link wherein the data is transmitted between the nodes in the form of packets made up of multiple bit frames. Each packet that is correctly received by the second node is acknowledged by means of a pair of multibit frames. These frames may be interleaved among the frames making up any outgoing data packet that is being transmitted by the second node. The technique employed provides unambiguous acknowledgment of each data packet and if a data packet is received incorrectly, the packet is available in a buffer in the first node for resending.

10. 发明申请

WO2006084783A2 CONNECTION ERROR AVOIDANCE IN APPARATUS CONNECTED TO A POWER SUPPLY 审中-公开
标题翻译：连接到电源的设备中的连接错误避免
公开(公告)号：WO2006084783A2
公开(公告)日：2006-08-17
申请号：PCT/EP2006/050286
申请日：2006-01-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HYATT, Steve, John , JUDD, Ian, David , NICHOLSON, Robert, Bruce , QUELCH, Paul, Jonathan , RANDLE, Stephen, Arthur , SCALES, William, James
发明人： HYATT, Steve, John , JUDD, Ian, David , NICHOLSON, Robert, Bruce , QUELCH, Paul, Jonathan , RANDLE, Stephen, Arthur , SCALES, William, James
IPC分类号： G06F1/26
CPC分类号： G06F11/2289 , Y10T307/615
摘要： A logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, comprises: a pattern-generating component for generating an identifiable pattern for a patterned load to be drawn from a power supply connection; a load-drawing component, responsive to the pattern-generating component, 10 for drawing the patterned load from the power supply connection; and a testing component at the power consumer apparatus for testing across a signal connection for a responsive supply to satisfy demand for the patterned load by the power supply apparatus. The logic arrangement may further be embodied as a system or as a computer program.
摘要翻译：用于减少功率消耗装置与电源装置之间的连接中的误差的发生的逻辑布置包括：图案生成部件，用于生成图案负载的可识别图案，所述图案负载将从电源连接; 响应于图案生成组件10，用于从电源连接中拉出图案化负载的负载绘制组件; 以及在功率消耗装置处的测试组件，用于在响应电源的信号连接上进行测试以满足电源装置对图案化负载的需求。该逻辑装置还可以体现为系统或计算机程序。

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