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    • 2. 发明申请
    • SYSTEM AND METHOD FOR PROVIDING CONFIGURABLE LATENCY AND/OR DENSITY IN MEMORY DEVICES
    • 用于在存储器件中提供可配置的延迟和/或密度的系统和方法
    • WO2010151481A1
    • 2010-12-29
    • PCT/US2010/039064
    • 2010-06-17
    • MICRON TECHNOLOGY, INC.FARRELL, Todd D.JOHNSON, Christopher S.
    • FARRELL, Todd D.JOHNSON, Christopher S.
    • G06F13/16G11C7/10
    • G06F13/1647G11C11/4087G11C2207/2272
    • Memory devices (10), memory controllers (20), methods, and systems are provided, such as methods for masking the row cycle latency time of a memory array (22). In one embodiment, a memory device (10) that is configurable to operate in full or reduced density modes is provided. In a reduced density mode, certain banks within the memory array (22) function as duplicate memory banks associated with an addressable memory bank. Write operations (140) performed in the reduced density mode may write a data segment to an addressed memory bank as well as its associated duplicate banks. When repeated read requests (160) are issued for the data segment, the read requests (160) may be interleaved between the addressed bank and its duplicate banks, thereby masking the row cycle time of each physical bank. That is, the interval between each read out of the data segment from the memory array (22) will appear to be less than the row cycle time.
    • 提供存储器件(10),存储器控制器(20),方法和系统,诸如用于掩蔽存储器阵列(22)的行周期等待时间的方法。 在一个实施例中,提供了可配置为以全密度或低密度模式操作的存储器件(10)。 在减小密度模式中,存储器阵列(22)内的某些存储体用作与可寻址存储体相关联的重复存储体。 以减小密度模式执行的写操作(140)可以将数据段写入寻址的存储体以及其相关联的重复存储体。 当针对数据段发出重复的读请求(160)时,读请求(160)可以在寻址的存储体与其重复存储体之间进行交织,由此屏蔽每个物理存储体的行周期时间。 也就是说,从存储器阵列(22)读出的每个数据段之间的间隔将看起来小于行周期时间。