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1. 发明申请

WO2006075206A2 DIGITAL CLOCK DIVIDING CIRCUIT 审中-公开
标题翻译：数字时钟分频电路
公开(公告)号：WO2006075206A2
公开(公告)日：2006-07-20
申请号：PCT/IB2005003761
申请日：2005-12-13
申请人： NOKIA CORP , NOKIA INC , HELIO PETRI
发明人： HELIO PETRI
IPC分类号： H03K27/00 , H04B1/40
CPC分类号： H03K23/54
摘要： Disclosed is a digital dividing circuit for dividing a timing signal. Memory elements are disposed in opposed pairs at opposed sides of a data loop. Each memory element is clocked to change the data bit it stores on each clock pulse. At least two opposed nodes along the data loop are coupled to one another by a memory content check MCC sub-circuit. The MCC checks for a desired relation between nodes. If the desired relation exists, then data values and phases rotate a step around the data loop during each clock cycle. If the desired relation does not exist, then the data value on one node is used to correct the data value on the opposed node so to achieve the desired relation. The clock signal is divided based on the number of memory elements around the data loop, and some or all pairs of opposed memory elements maybe coupled through the MCC.
摘要翻译：公开了一种用于划分定时信号的数字分频电路。存储器元件在数据环路的相对侧以相对的对布置。每个存储器单元都被计时以改变其在每个时钟脉冲上存储的数据位。沿数据回路的至少两个相对的节点通过存储器内容检查MCC子电路相互耦合。 MCC检查节点之间的期望关系。如果存在所需关系，则数据值和相位在每个时钟周期内围绕数据循环旋转一步。如果所需关系不存在，则使用一个节点上的数据值来校正相对节点上的数据值，以实现所需的关系。时钟信号基于数据环路周围的存储器元件的数量被划分，并且一些或所有对的相对存储器元件可以通过MCC耦合。

2. 发明申请

WO2006070224A1 VCO CENTER FREQUENCY TUNING AND LIMITING GAIN VARIATION 审中-公开
标题翻译： VCO中心频率调谐和限幅增益变化
公开(公告)号：WO2006070224A1
公开(公告)日：2006-07-06
申请号：PCT/IB2005/003396
申请日：2005-11-14
申请人： NOKIA CORPORATION , NOKIA INC. , VAANANEN, Paavo , HELIO, Petri
发明人： VAANANEN, Paavo , HELIO, Petri
IPC分类号： H03L7/189 , H03J7/06 , H03L7/099
CPC分类号： H03L7/087 , H03J7/023 , H03J7/10 , H03J2200/10 , H03J2200/29 , H03J2200/36 , H03L7/099
摘要： This invention describes a method for simultaneous precise center frequency tuning and limiting a gain variation of a voltage controlled oscillator (VCO) of a phase locked loop (PLL) of an electronic device (e.g., a communication device, a mobile electronic device, a mobile phone, etc.). The invention utilizes frequency measurements and arithmetical optimizations. More specifically, the invention implementation is based on an analysis which includes measuring a frequency of a VCO and calculating a gain of the voltage controlled oscillator (VCO) using a predetermined criterion. The key element for implementing said analysis is a control and arithmetic block. The present invention can be used in any radio architecture that requires limiting of the VCO gain variation and tuning its center frequency.
摘要翻译：本发明描述了一种用于同时精确的中心频率调谐和限制电子设备的锁相环（PLL）的压控振荡器（VCO）的增益变化的方法（例如，通信设备，移动电子设备，移动设备电话等）。本发明利用频率测量和算术优化。更具体地说，本发明的实现基于包括测量VCO的频率并使用预定标准计算压控振荡器（VCO）的增益的分析。实现所述分析的关键要素是控制和算术块。本发明可以用于需要限制VCO增益变化并调整其中心频率的任何无线电架构中。

3. 发明申请

WO2006075206A3 DIGITAL CLOCK DIVIDING CIRCUIT 审中-公开
公开(公告)号：WO2006075206A3
公开(公告)日：2006-07-20
申请号：PCT/IB2005/003761
申请日：2005-12-13
申请人： NOKIA CORPORATION , NOKIA, INC. , HELIO, Petri
发明人： HELIO, Petri
IPC分类号： H03K27/00 , H04B1/40
摘要： Disclosed is a digital dividing circuit for dividing a timing signal. Memory elements are disposed in opposed pairs at opposed sides of a data loop. Each memory element is clocked to change the data bit it stores on each clock pulse. At least two opposed nodes along the data loop are coupled to one another by a memory content check MCC sub-circuit. The MCC checks for a desired relation between nodes. If the desired relation exists, then data values and phases rotate a step around the data loop during each clock cycle. If the desired relation does not exist, then the data value on one node is used to correct the data value on the opposed node so to achieve the desired relation. The clock signal is divided based on the number of memory elements around the data loop, and some or all pairs of opposed memory elements maybe coupled through the MCC.

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