专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011081843A2 ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER 审中-公开
标题翻译：使用存储器控制器的稳健的存储器链接测试
公开(公告)号：WO2011081843A2
公开(公告)日：2011-07-07
申请号：PCT/US2010/059823
申请日：2010-12-10
申请人： INTEL CORPORATION , SPRY, Bryan L. , SCHOENBORN, Theodore Z. , ABRAHAM, Philip , MOZAK, Christopher P. , ELLIS, David G. , NEJEDLO, Jay J. , QUERBACH, Bruce , GREENFIELD, Zvika , GHATTAS, Rony , THOLIYIL, Jayasekhar , LUCAS, Charles D. , YUNKER, Christopher E.
发明人： SPRY, Bryan L. , SCHOENBORN, Theodore Z. , ABRAHAM, Philip , MOZAK, Christopher P. , ELLIS, David G. , NEJEDLO, Jay J. , QUERBACH, Bruce , GREENFIELD, Zvika , GHATTAS, Rony , THOLIYIL, Jayasekhar , LUCAS, Charles D. , YUNKER, Christopher E.
IPC分类号： G11C29/10
CPC分类号： G11C29/08 , G11C29/10 , G11C29/44
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译：引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。还公开了地址图案生成电路。

2. 发明申请

WO2014004748A1 ROW HAMMER REFRESH COMMAND 审中-公开
公开(公告)号：WO2014004748A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/048016
申请日：2013-06-26
申请人： INTEL CORPORATION , BAINS, Kuljit , HALBERT, John B. , MOZAK, Christopher P. , SCHOENBORN, Theodore Z. , GREENFIELD, Zvika
发明人： BAINS, Kuljit , HALBERT, John B. , MOZAK, Christopher P. , SCHOENBORN, Theodore Z. , GREENFIELD, Zvika
IPC分类号： G11C11/401 , G11C11/406
CPC分类号： G11C11/4091 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G06F2212/7211 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as "hammered" or a "row hammer event"), physically adjacent row (a "victim" row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
摘要翻译：内存控制器发出目标刷新命令。存储器件的特定行可以是重复访问的目标。当行在时间阈值（也称为“锤击”或“行锤事件”）中被重复访问时，物理上相邻的行（“受害者”行）可能经历数据损坏。存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

3. 发明申请

WO2013002789A1 METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND PROTECTION AGAINST REPLAY ATTACKS 审中-公开
标题翻译：用于内容加密的方法和装置，具有完整的检查和防止重复攻击的保护
公开(公告)号：WO2013002789A1
公开(公告)日：2013-01-03
申请号：PCT/US2011/042413
申请日：2011-06-29
申请人： INTEL CORPORATION , GUERON, Shay , SAVAGAONKAR, Uday , MCKEEN, Francis X. , ROZAS, Carlos V. , DURHAM, David M. , DOWECK, Jacob , MULLA, Ofir , ANATI, Ittai , GREENFIELD, Zvika , MAOR, Moshe
发明人： GUERON, Shay , SAVAGAONKAR, Uday , MCKEEN, Francis X. , ROZAS, Carlos V. , DURHAM, David M. , DOWECK, Jacob , MULLA, Ofir , ANATI, Ittai , GREENFIELD, Zvika , MAOR, Moshe
IPC分类号： G06F21/24 , G06F21/02 , G06F12/14
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/00 , G06F21/64 , H04L9/0637 , H04L9/3242
摘要： A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a "time stamp" indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a "time stamp" indicator associated with the cache line. The "time stamp indicator" is stored in a processor.
摘要翻译：提供了一种提供加密完整性检查和重放保护以防止对系统存储器的硬件攻击的方法和装置。分组密码的操作模式增强了标准的XTS-AES操作模式，通过扩展调整以包括“时间戳”指示符来执行存储器加密。基于树的重放保护方案使用标准的XTS-AES来加密系统内存中的高速缓存行的内容。高速缓存行的消息认证码（MAC）使用增强型XTS-AES和与高速缓存行相关联的“时间戳”指示符进行加密。 “时间戳指示符”存储在处理器中。

4. 发明申请

WO2014105134A1 TRAINING FOR MAPPING SWIZZLED DATA COMMAND/ADDRESS SIGNALS 审中-公开
标题翻译：训练用于映射数据命令/地址信号
公开(公告)号：WO2014105134A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046406
申请日：2013-06-18
申请人： INTEL CORPORATION , KOSTINSKY, Alexey , GREENFIELD, Zvika , MOZAK, Christopher P. , KONEV, Pavel , FOMENKO, Olga
发明人： KOSTINSKY, Alexey , GREENFIELD, Zvika , MOZAK, Christopher P. , KONEV, Pavel , FOMENKO, Olga
IPC分类号： G06F13/14 , G06F12/00 , G11C11/4096
CPC分类号： G11C7/1072 , G11C7/1063 , G11C7/20 , G11C11/4072 , G11C29/023 , G11C29/028 , G11C2207/105 , G11C2207/2254
摘要： Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.
摘要翻译：数据引脚映射和延迟训练技术。在存储设备的命令/地址（CA）总线上检测到有效值。响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位）引脚。分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。

5. 发明申请

WO2011081843A3 ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER 审中-公开
标题翻译：使用存储器控制器进行稳健的存储器链接测试
公开(公告)号：WO2011081843A3
公开(公告)日：2011-11-10
申请号：PCT/US2010059823
申请日：2010-12-10
申请人： INTEL CORP , SPRY BRYAN L , SCHOENBORN THEODORE Z , ABRAHAM PHILIP , MOZAK CHRISTOPHER P , ELLIS DAVID G , NEJEDLO JAY J , QUERBACH BRUCE , GREENFIELD ZVIKA , GHATTAS RONY , THOLIYIL JAYASEKHAR , LUCAS CHARLES D , YUNKER CHRISTOPHER E
发明人： SPRY BRYAN L , SCHOENBORN THEODORE Z , ABRAHAM PHILIP , MOZAK CHRISTOPHER P , ELLIS DAVID G , NEJEDLO JAY J , QUERBACH BRUCE , GREENFIELD ZVIKA , GHATTAS RONY , THOLIYIL JAYASEKHAR , LUCAS CHARLES D , YUNKER CHRISTOPHER E
IPC分类号： G11C29/10
CPC分类号： G11C29/08 , G11C29/10 , G11C29/44
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译：引入了用于记忆链路的REUT（可靠的电气统一测试），可加速测试，工具开发和调试。此外，它还提供了具有足够性能的培训挂钩，以供BIOS使用，以训练过去实现时无法实现的参数和条件。地址模式生成电路也被公开。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式