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    • 4. 发明申请
    • TRAINING FOR MAPPING SWIZZLED DATA COMMAND/ADDRESS SIGNALS
    • 训练用于映射数据命令/地址信号
    • WO2014105134A1
    • 2014-07-03
    • PCT/US2013/046406
    • 2013-06-18
    • INTEL CORPORATIONKOSTINSKY, AlexeyGREENFIELD, ZvikaMOZAK, Christopher P.KONEV, PavelFOMENKO, Olga
    • KOSTINSKY, AlexeyGREENFIELD, ZvikaMOZAK, Christopher P.KONEV, PavelFOMENKO, Olga
    • G06F13/14G06F12/00G11C11/4096
    • G11C7/1072G11C7/1063G11C7/20G11C11/4072G11C29/023G11C29/028G11C2207/105G11C2207/2254
    • Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.
    • 数据引脚映射和延迟训练技术。 在存储设备的命令/地址(CA)总线上检测到有效值。 响应于CA总线上的检测值,该模式的第一部分(高相位)经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值,经由数据引脚的第二子集在存储器件上传送图案(低相位)的第二部分。 信号在存储器控制器处被从数据引脚采样,同时正在发送CA模式,以通过分析采样数据的第一和第二子集来获得第一存储器件的采样(高相位)和第二存储器件的采样(低相位) 引脚。 分析结合CA总线上传输模式的知识,找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练,并且不使用二进制数据引脚映射知识。