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1. 发明申请

WO2006115928A1 TRANSCEIVER WITH DIGITAL INTERFACE AND EVENT MANAGER 审中-公开
标题翻译：数字接口和事件管理器的收发器
公开(公告)号：WO2006115928A1
公开(公告)日：2006-11-02
申请号：PCT/US2006/014700
申请日：2006-04-19
申请人： SILICON LABORATORIES INC. , GREEN, Brian, D. , ADIREDDY, Srihari , LIM, Lysander , GANTI, Ramkishore
发明人： GREEN, Brian, D. , ADIREDDY, Srihari , LIM, Lysander , GANTI, Ramkishore
IPC分类号： H04B1/40
CPC分类号： H04B1/40
摘要： In one embodiment, the present invention includes a method for receiving at a transceiver from a baseband processor digital control information that includes both event and schedule information, storing the digital control information in a storage of the transceiver, and operating the transceiver according to the event and schedule information.
摘要翻译：在一个实施例中，本发明包括一种用于从基带处理器接收数据控制信息的方法，所述数字控制信息包括事件和时间表信息，将数字控制信息存储在收发器的存储器中，并根据事件操作收发器和时间表信息。

2. 发明申请

WO2012152903A1 MULTI-STANDARD TRANSCEIVER ARCHITECTURE WITH COMMON BALUN AND MIXER 审中-公开
标题翻译：多标准收发器架构与普通巴伦和混频器
公开(公告)号：WO2012152903A1
公开(公告)日：2012-11-15
申请号：PCT/EP2012/058719
申请日：2012-05-11
申请人： ST-ERICSSON SA , GANTI, Ramkishore , RANGANATHAN, Sanjeev , SRIDHARAN, Srinath
发明人： GANTI, Ramkishore , RANGANATHAN, Sanjeev , SRIDHARAN, Srinath
IPC分类号： H04B1/00 , H04B1/40 , H04B1/04
CPC分类号： H04W88/06 , H04B1/0053 , H04B1/0458 , H04B1/0483 , H04B1/406
摘要： A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.
摘要翻译：多标准收发器包括公共平衡 - 不平衡变压器，控制器，至少一个第一开关和至少一个第二开关。普通的不平衡变压器包括初级线圈和次级线圈。所述至少一个第一开关响应于由控制器提供的控制信号将平衡 - 不平衡变换器的初级线圈连接到与第一通信标准相关联的第一信号路径或者与第二通信标准相关联的第二信号路径。响应于由控制器提供的控制信号，至少一个第二开关将平衡 - 不平衡变换器的次级线圈连接到与第一通信标准相关联的第一放大路径，或连接到与第二通信标准相关联的第二放大路径。公共混频器被配置为根据选择了哪个通信标准来向信号路径中的一个提供上变频信号。

3. 发明申请

WO2004059855A1 BANDPASS DELTA SIGMA TRUNCATOR AND METHOD OF TRUNCATING A MULTI-BIT DIGITAL SIGNAL 审中-公开
标题翻译： BANDPASS DELTA SIGMA TRUNCATOR AND METHOD OF TRUNCATING A MULTI BIT DIGITAL SIGNAL
公开(公告)号：WO2004059855A1
公开(公告)日：2004-07-15
申请号：PCT/US2002/041396
申请日：2002-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GANTI, Ramkishore , ESHRAGHI, Aria
发明人： GANTI, Ramkishore , ESHRAGHI, Aria
IPC分类号： H04B1/10
CPC分类号： H03M7/3017 , H03M7/3026 , H03M7/3042
摘要： A bandpass delta sigma truncator that truncates multi-bit digital input signals to digital output signals (24) having a selected number of the most significant data bits of the digital input signals and a method of truncating multi-bit digital signals. The remaining least significant data bits (3) of the input signals are (a) time delayed (26) by a period of time equal to the time between successive input signals and multiplied by a number (30) related to the ratio of a selected frequency to the frequency of the input signals and the results of the multiplication are added (32) to signs extensions (11) of the input signals, and (b) time delayed by a period of time equal to twice the time between successive input signals and after inversion (28) are added (32) to the sign extensions of the input signals.
摘要翻译：一种将多位数字输入信号截断为数字输入信号的选定数量的最高有效数据位的数字输出信号（24）的带通三角Σ截断器以及截断多位数字信号的方法。输入信号的剩余最低有效数据位（3）是（a）时间延迟（26）等于连续输入信号之间的时间的时间段，并乘以与所选择的比例相关的数字（30）将输入信号的频率和乘法结果的频率相加（32）到输入信号的符号扩展（11），以及（b）时间延迟等于连续输入信号之间的时间的两倍的时间并且在反相（28）之后（32）加到输入信号的符号扩展上。

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