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1. 发明申请

WO2009085536A2 HIGH PERFORMANCE ETHERNET NETWORKING UTILIZING EXISTING FIBRE CHANNEL FABRIC HBA 审中-公开
标题翻译：利用现有光纤通道结构HBA的高性能以太网联网
公开(公告)号：WO2009085536A2
公开(公告)日：2009-07-09
申请号：PCT/US2008/085257
申请日：2008-12-02
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , HIRATA, Kenneth, Hiroshi , BERMAN, Stuart, Bruce
发明人： HIRATA, Kenneth, Hiroshi , BERMAN, Stuart, Bruce
IPC分类号： H04J3/16
CPC分类号： H04L49/351 , H04L12/462 , H04L29/12801 , H04L29/12839 , H04L49/357 , H04L61/6004 , H04L61/6022
摘要： This is directed to providing Fibre Channel over Ethernet communication. For example a Fibre Channel over Ethernet (FCoE) enabled device (such as a computer) may include a Fibre Channel over Ethernet Adapter (FCoEA). The FCoEA may include an HBA module. The HBA module may be configured to communicate over the Fibre Channel protocol. The FCoE enabled device may process and encapsulate the HBA module's communication in order to send them over an Ethernet network instead. The FCoE enabled device may process communications directed to various Fibre Channel fabric services by utilizing existing Ethernet services, such as an iSNS server. Thus, the FCoE enabled device can emulate a Fibre Channel network for the HBA module using the Ethernet network and one or more Existing Ethernet services/servers.
摘要翻译：这是针对提供以太网光纤通道通信。例如，支持以太网的光纤通道（FCoE）设备（例如计算机）可能包括以太网光纤通道适配器（FCoEA）。 FCoEA可能包含HBA模块。 HBA模块可以被配置为通过光纤通道协议进行通信。启用FCoE的设备可以处理和封装HBA模块的通信，以便通过以太网网络发送它们。启用FCoE的设备可以利用现有的以太网服务（例如iSNS服务器）处理针对各种光纤通道结构服务的通信。因此，支持FCoE的设备可以使用以太网网络和一个或多个现有以太网服务/服务器为HBA模块模拟光纤通道网络。

2. 发明申请

WO2006110845A2 METHOD AND APPARATUS FOR SATA TUNNELING OVER FIBRE CHANNEL 审中-公开
标题翻译： SATA隧道在光纤通道上的方法和装置
公开(公告)号：WO2006110845A2
公开(公告)日：2006-10-19
申请号：PCT/US2006/013716
申请日：2006-04-11
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , WARREN, Bruce Gregory , NOTTBERG, Curtis Edward , MIES, Carl Joseph , BOWMAN, Kevin Dale , SHAH, Noumaan Ahmed , FRANCO, Gary Lynn
发明人： WARREN, Bruce Gregory , NOTTBERG, Curtis Edward , MIES, Carl Joseph , BOWMAN, Kevin Dale , SHAH, Noumaan Ahmed , FRANCO, Gary Lynn
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/067 , H04L67/1097 , H04L69/08
摘要： A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send data to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fibre Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de- encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.
摘要翻译：公开了一种用于在FC SAN中使用SATA驱动器的系统。要通过FC SAN将数据发送到SATA驱动器，主机将通过标准FC链路封装在FC帧中的SCSI命令发送到光纤通道附加SATA隧道（FAST）RAID控制器，其中SCSI命令从FC中解封装框架并转换为SATA FIS。然后将SATA FIS封装到FC帧中。执行这些功能的IOC被称为FAST IOC。 SATA封装的FC帧通过另一个标准FC链路发送到多个磁盘驱动器机箱。 FC框架由磁盘驱动器机箱中的FAST开关拆封，以检索SATA FIS，并通过SATA连接将SATA FIS发送到SATA驱动器。

3. 发明申请

WO2005036313A2 QUEUE REGISTER CONFIGURATION STRUCTURE 审中-公开
标题翻译：队列寄存器配置结构
公开(公告)号：WO2005036313A2
公开(公告)日：2005-04-21
申请号：PCT/US2004/025387
申请日：2004-08-26
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , DUCKMAN, David, James
发明人： DUCKMAN, David, James
IPC分类号： G06F
CPC分类号： G06F9/546 , H04L67/1097 , H04L69/329
摘要： Generalized queues and specialized registers associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors. The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of the entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notification of queue and other conditions, selectively in receiving and generating conditions, and the ability to combine data transfer and particular condition notification in the same attention register.
摘要翻译：公开了与广义队列相关联的广义队列和专用寄存器，用于协调两个紧密耦合的处理器之间的信息传递。可以调整队列的容量以匹配当前的环境，对发送和接收处理器之间商定的条目的大小没有限制，并且对条目数量或条目的限制没有实际限制出现。此外，专用寄存器允许立即通知队列和其他条件，选择性地接收和生成条件，以及将数据传输和特定条件通知组合在同一关注寄存器中的能力。

4. 发明申请

WO2005017662A2 METHODS AND APPARATUS FOR SWITCHING FIBRE CHANNEL ARBITRATED LOOP SYSTEMS 审中-公开
标题翻译：用于切换光纤通道仲裁系统的方法和装置
公开(公告)号：WO2005017662A2
公开(公告)日：2005-02-24
申请号：PCT/US2004/022131
申请日：2004-07-09
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , WARREN, Bruce, Gregory , GOODWIN, William , MIES, Carl , JOHNSON, Bruce, E. , WHITE, Michael, L. , ENG, Warren
发明人： WARREN, Bruce, Gregory , GOODWIN, William , MIES, Carl , JOHNSON, Bruce, E. , WHITE, Michael, L. , ENG, Warren
IPC分类号： G06F
CPC分类号： H04L12/4637 , H04L12/433
摘要： Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS. In yet other aspects, the system ensures device access fairness through one or more techniques, including a rotating priority system, a counter to count the number of OPNs, especially sequential OPNs, and/or priority based on port type. Device zoning may be implemented. In one implementation, the system includes trunking such that frames may be transferred on multiple ports.
摘要翻译：在多个光纤通道环路设备之间提供用于交换光纤通道仲裁环路系统的方法和设备。在本发明的一个方面，系统至少部分地基于仲裁的循环原语来切换。示例性互连系统可以包括第一端口和第二端口，两者都包括用于监视某些仲裁环路原语的端口逻辑，连接装置，包括由ALPA地址及其相关联的端口组成的路由表的路由确定装置，路由确定装置耦合到每个端口和连接装置，其中连接装置基于仲裁的循环基元在端口之间创建路径。在一个实施例中，连接装置是交叉开关。导致交换机在端口之间创建路径的仲裁循环图元的示例包括以下一个或多个：ARB，OPN和CLS。在另一方面，该系统通过一种或多种技术来确保设备访问的公平性，包括旋转优先级系统，计数OPN数量的计数器，特别是连续的OPN，和/或基于端口类型的优先级。可以实现设备分区。在一个实现中，系统包括中继，使得帧可以在多个端口上传送。

5. 发明申请

WO2005008406A2 METHODS AND APPARATUS FOR DEVICE ZONING IN FIBRE CHANNEL ARBITRATED LOOP SYSTEMS 审中-公开
标题翻译：光纤通道仲裁系统中设备分区的方法与设备
公开(公告)号：WO2005008406A2
公开(公告)日：2005-01-27
申请号：PCT/US2004/021983
申请日：2004-07-09
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , MIES, Carl , WARREN, Bruce, Gregory
发明人： MIES, Carl , WARREN, Bruce, Gregory
IPC分类号： G06F
CPC分类号： H04L12/42 , H04L12/433 , H04L45/18 , H04L49/357
摘要： Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS. In yet other aspects., the system ensures device access fairness through one or more techniques, including a rotating priority system, a counter to count the number of OPNs, especially sequential OPNs, and/or priority based on port type. Device zoning may be implemented. In one implementation, the system includes trunking such that frames may be transferred on multiple ports.
摘要翻译：在多个光纤通道环路设备之间提供用于交换光纤通道仲裁环路系统的方法和设备。在本发明的一个方面，系统至少部分地基于仲裁的循环原语来切换。示例性互连系统可以包括第一端口和第二端口，两者都包括用于监视某些仲裁环路原语的端口逻辑，连接装置，包括由ALPA地址及其相关联的端口组成的路由表的路由确定装置，路由确定装置耦合到每个端口和连接装置，其中连接装置基于仲裁的循环基元在端口之间创建路径。在一个实施例中，连接装置是交叉开关。导致交换机在端口之间创建路径的仲裁循环图元的示例包括以下一个或多个：ARB，OPN和CLS。在其他方面，系统通过一种或多种技术来确保设备访问的公平性，包括旋转优先级系统，计数OPN数量的计数器，特别是顺序OPN，和/或基于端口类型的优先级。可以实现设备分区。在一个实现中，系统包括中继，使得帧可以在多个端口上传送。

6. 发明申请

WO2004088461A2 LOCAL EMULATION OF DATA RAM UTILIZING WRITE-THROUGH CACHE HARDWARE WITHIN A CPU MODULE 审中-公开
标题翻译：在CPU模块中使用写入式高速缓存硬件的数据RAM的本地仿真
公开(公告)号：WO2004088461A2
公开(公告)日：2004-10-14
申请号：PCT/US2004/009196
申请日：2004-03-26
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION
发明人： SPENCER, Thomas, Vincent
IPC分类号： G06F
CPC分类号： G06F12/0802 , G06F12/0888 , G06F12/126 , G06F2212/2515
摘要： In a processor module having a local software visible data memory and a write through cache connected to an external memory space external to the processor module over a bus, a method and apparatus for supplementing the local software visible data memory utilizing the write through cache is disclosed which may comprise: a processor bus interface and memory management unit adapted to detect a processor write operation to a preselected location in the external memory space that is not currently a cached address line, that will cause a cache miss, to decode the write operation to the preselected external memory space location as a RAM emulation write operation and to place in the cache pseudo data at the respective address line in the cache, without executing a fetch and store from the actual external memory location in response to the cache miss. The method and apparatus may further comprise the processor bus interface and memory management unit further adapted to subsequently ignore the write through command from the processor when the processor writes to the address without a cache miss. The external memory space may include a cacheable portion of external memory space and a non-cacheable portion of the external memory space; and, the preselected external memory space may be located within the cacheable portion of the external memory space. The module may be implemented on an integrated circuit and comprise a portion of a computer and communication link interface and may include a plurality of modules and may be contained on a host bus adapter card.
摘要翻译：在具有本地软件可视数据存储器和通过总线连接到处理器模块外部的外部存储器空间的写入高速缓存的处理器模块中，公开了一种利用写入高速缓存来补充本地软件可见数据存储器的方法和装置其可以包括：处理器总线接口和存储器管理单元，其适于检测对外部存储器空间中的当前未被缓存的地址线的预选位置（将导致高速缓存未命中）的处理器写入操作，以将写入操作解码为预选的外部存储器空间位置作为RAM仿真写入操作，并且在高速缓存中的相应地址线处放置在高速缓存伪数据中，而不执行响应于高速缓存未命中的实际外部存储器位置的获取和存储。该方法和装置还可以包括处理器总线接口和存储器管理单元，该处理器总线接口和存储器管理单元进一步适于随后当处理器写入地址而忽略高速缓存时随后忽略来自处理器的写入命令。外部存储器空间可以包括外部存储器空间的可高速缓存部分和外部存储器空间的不可高速缓存部分; 并且预选的外部存储器空间可以位于外部存储器空间的可高速缓存部分内。该模块可以在集成电路上实现并且包括计算机的一部分和通信链路接口，并且可以包括多个模块并且可以包含在主机总线适配器卡上。

7. 发明申请

WO2006110844A3 TUNNELING SATA TARGETS THROUGH FIBRE CHANNEL 审中-公开
公开(公告)号：WO2006110844A3
公开(公告)日：2006-10-19
申请号：PCT/US2006/013715
申请日：2006-04-11
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , CRESPI, David, Andrew , MIES, Carl, Joseph , WARREN, Bruce, Gregory , FRANCO, Gary, Lynn
发明人： CRESPI, David, Andrew , MIES, Carl, Joseph , WARREN, Bruce, Gregory , FRANCO, Gary, Lynn
IPC分类号： G06F15/16
摘要： A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send SATA FISs to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fibre Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de- encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.

8. 发明申请

WO2005098623A2 PREREQUISITE-BASED SCHEDULER 审中-公开
标题翻译：基于优先级的调度器
公开(公告)号：WO2005098623A2
公开(公告)日：2005-10-20
申请号：PCT/US2005/010804
申请日：2005-03-30
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , JONES, Marc, Timothy , NOTTBERG, Curtis, Edward , SIEWERT, Samuel, Burk
发明人： JONES, Marc, Timothy , NOTTBERG, Curtis, Edward , SIEWERT, Samuel, Burk
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/5011
摘要： A prerequisite-based scheduler is disclosed which takes into account system resource prerequisites for execution. Tasks are only scheduled when they can successfully run to completion and therefore a task, once dispatched, is guaranteed not to become blocked. In a prerequisite table, tasks are identified horizontally, and resources needed for the tasks are identified vertically. At the bottom of the table is the system state, which represents the current state of all resources in the system. If a Boolean AND operation is applied to the task prerequisite row and the system state, and if the result is the same as the prerequisite row, then the task is dispatchable. In one embodiment of the present invention, the prerequisite based scheduler (dispatcher) walks through the prerequisite table from top to bottom until a task is found whose prerequisites are satisfied by the system state. Once found, this task is dispatched.
摘要翻译：公开了基于先决条件的调度器，其考虑了用于执行的系统资源先决条件。任务只有在成功运行到完成时才安排，因此一旦派遣，任务就被保证不被阻止。在先决条件表中，任务被水平识别，并且垂直地识别任务所需的资源。表的底部是系统状态，表示系统中所有资源的当前状态。如果将布尔AND运算应用于任务前提行和系统状态，并且如果结果与先决条件行相同，则任务可分派。在本发明的一个实施例中，基于先决条件的调度器（调度器）从上到下遍历前提表，直到发现任务被系统状态满足的前提条件。一旦找到，这个任务被调度。

9. 发明申请

WO2005024556A2 DIRECT MEMORY ACCESS FROM HOST WITHOUT PROCESSOR INTERVENTION 审中-公开
标题翻译：没有加工者干预的直接存储器从主机访问
公开(公告)号：WO2005024556A2
公开(公告)日：2005-03-17
申请号：PCT/US2004/025252
申请日：2004-08-04
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , MILLER, Eddie , DUCKMAN, David, James , BUTLER, Jim, Donald , JIN, Daming , TANG, John, Sui-Kei
发明人： MILLER, Eddie , DUCKMAN, David, James , BUTLER, Jim, Donald , JIN, Daming , TANG, John, Sui-Kei
IPC分类号： G06F
CPC分类号： G06F13/385 , G06F13/28
摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the assistance of a microprocessor located on the peripheral device. In a preferred embodiment, new host registers are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to access the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.
摘要翻译：一种用于允许主机设备（例如，服务器）在位于外围设备上的微处理器的帮助下对位于外围设备（例如，HBA）上的外围存储器（例如，闪存）进行编程的直接访问的方法和系统。在优选实施例中，新的主机寄存器被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。主机设备读取和写入主机寄存器，这导致适当的控制器硬件相应地访问外设非易失性存储器。通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。

10. 发明申请

WO2005024555A2 MULTI-CHANNEL MEMORY ACCESS ARBITRATION METHOD AND SYSTEM 审中-公开
标题翻译：多通道存储器访问仲裁方法和系统
公开(公告)号：WO2005024555A2
公开(公告)日：2005-03-17
申请号：PCT/US2004/025251
申请日：2004-08-04
申请人： EMULEX DESIGN & MANUFACTURING CORPORATION , MILLER, Eddie , DUCKMAN, David, James , BUTLER, Jim, Donald , HUYNH, Khanh, Hue
发明人： MILLER, Eddie , DUCKMAN, David, James , BUTLER, Jim, Donald , HUYNH, Khanh, Hue
IPC分类号： G06F
CPC分类号： G06F9/526
摘要： A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.
摘要翻译：一种用于允许灵活控制多个请求者对共享存储器的访问的方法和系统。在优选实施例中，本发明仲裁在多个主机信道和HBA微处理器之间的HBA上对闪存的访问，并且通过允许将许可锁定在由闪存写协议定义的时间段内，在写周期期间消除闪存的争用可能性和时机。

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