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1. 发明申请

WO2005031458A2 FORMING PARTIAL-DEPTH FEATURES IN POLYMER FILM 审中-公开
标题翻译：在聚合物膜中形成局部深度特征
公开(公告)号：WO2005031458A2
公开(公告)日：2005-04-07
申请号：PCT/US2004/031732
申请日：2004-09-27
申请人： FLIP CHIP TECHNOLOGIES, L.L.C. , JOHNSON, Michael, E. , ELENIUS, Peter
发明人： JOHNSON, Michael, E. , ELENIUS, Peter
IPC分类号： G03F
CPC分类号： G03F1/50
摘要： A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101-2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. § 1.72(b).
摘要翻译：用于使用曝光工具在芯片级封装（200）的晶片上的可光成像聚合物层（412）中产生局部深度特征（712和912）的光掩模（1900），所述曝光工具能够分辨临界尺寸或更大的尺寸，具有多条铬线（2101-2103）。每条铬线具有小于临界尺寸的宽度（2105），并且多条铬线中的每条铬线间隔开的距离小于临界尺寸。多条铬线通过聚合物层厚度的一部分产生单个局部深度特征，例如通孔。或者，光掩模具有多个铬环（2206），每个铬环具有小于临界尺寸的直径并且间隔小于产生局部深度特征的临界尺寸。光掩模也可以具有宽度大于临界尺寸的铬并且与其他铬间隔开大于临界尺寸的距离，其在整个聚合物膜的厚度上产生全深度特征。部分深度特征和全深度特征在单个系列的光成像步骤期间基本上同时产生。通过预先选择铬之间的尺寸，形状和距离，光掩模能够在聚合物层上刻出可识别的标记，改变聚合物层的厚度并改变聚合物层表面的光学性质。提交摘要的理解是，根据37 C.F.R，它不会用于解释或限制权利要求的范围或含义。＆教派; 1.72（b）所示。

2. 发明申请

WO2005031807A2 WAFER-LEVEL MOAT STRUCTURES 审中-公开
标题翻译：水平运动结构
公开(公告)号：WO2005031807A2
公开(公告)日：2005-04-07
申请号：PCT/US2004/031583
申请日：2004-09-27
申请人： FLIP CHIP TECHNOLOGIES, L.L.C. , JOHNSON, Michael, E. , ELENIUS, Peter , KIM, Deok Hoon
发明人： JOHNSON, Michael, E. , ELENIUS, Peter , KIM, Deok Hoon
IPC分类号： H01L
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05567 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
摘要翻译：晶片级CSP（200）包括来自晶片的至少一个管芯（202）。晶片级CSP具有多个焊球垫（206），每个焊球垫处的焊球（308）和围绕每个焊球的聚合物环（310）。在晶片级CSP的制造期间，在布置在晶片上的聚合物层（412）的表面中形成护城河（204）。当晶片被加热到焊球的回流温度时，从聚合物套环的临时液化剩余物（502）从聚合物套环流出。护城河作为物料流动的障碍，限制了液化时残留物扩散的距离。来自聚合物套环的残余物保留在由护城河限定的区域（314）内。全深的护城河（312）完全延伸穿过聚合物层。或者，部分深度护城河（712和912）部分地延伸穿过聚合物层。提交摘要的理解是，根据37 C.F.R.不会用于解释或限制权利要求的范围或含义。 §1.72（b）中。

3. 发明申请

WO2005031458A3 FORMING PARTIAL-DEPTH FEATURES IN POLYMER FILM 审中-公开
标题翻译：在聚合物膜中形成部分深度特征
公开(公告)号：WO2005031458A3
公开(公告)日：2005-07-14
申请号：PCT/US2004031732
申请日：2004-09-27
申请人： FLIP CHIP TECHNOLOGIES L L C , JOHNSON MICHAEL E , ELENIUS PETER
发明人： JOHNSON MICHAEL E , ELENIUS PETER
IPC分类号： G03C5/00 , G03F20060101 , G03F1/14 , G03F9/00 , G21K5/00
CPC分类号： G03F1/50
摘要： A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101-2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. § 1.72(b).
摘要翻译：一种光掩模（1900），用于使用能够分辨关键尺寸或更大尺寸的曝光工具在芯片级封装（200）的晶片上的可光成像聚合物层（412）中产生部分深度特征（712和912）具有多条铬线（2101-2103）。每个铬线具有小于临界尺寸的宽度（2105），并且多个铬线的每个铬线间隔开小于临界尺寸。多条铬线通过聚合物层的厚度的一部分产生单一部分深度特征，例如通孔。或者，光掩模具有多个铬圆（2206），每个铬圆的直径小于临界尺寸，并且间隔开小于临界尺寸，产生部分深度特征。光掩模还可以具有大于临界尺寸的宽度的铬，并且与其它铬隔开大于临界尺寸的距离，其通过聚合物膜的整个厚度产生全深度特征。部分深度特征和全深度特征在单个系列的光成像步骤期间基本上同时产生。通过预先选择铬之间的尺寸，形状和距离，光掩模能够在聚合物层上刻划可辨别的标记，改变聚合物层的厚度和改变聚合物层的表面的光学性质。提交摘要的理解是，根据37 C.F.R.不会将其用于解释或限制权利要求的范围或含义。 §1.72（b）。

4. 发明申请

WO2005031807A3 WAFER-LEVEL MOAT STRUCTURES 审中-公开
标题翻译：晶片级MOAT结构
公开(公告)号：WO2005031807A3
公开(公告)日：2005-06-23
申请号：PCT/US2004031583
申请日：2004-09-27
申请人： FLIP CHIP TECHNOLOGIES L L C , JOHNSON MICHAEL E , ELENIUS PETER , KIM DEOK HOON
发明人： JOHNSON MICHAEL E , ELENIUS PETER , KIM DEOK HOON
IPC分类号： H01L20060101 , H01L21/44 , H01L21/60 , H01L21/66 , H01L23/31 , H01L23/485
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05567 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
摘要翻译：晶圆级CSP（200）包括来自晶圆的至少一个管芯（202）。晶圆级CSP具有多个焊球垫（206），每个焊球垫处的焊球（308）以及每个焊球周围的聚合物套环（310）。在制造晶片级CSP期间，在设置在晶片上的聚合物层（412）的表面中形成沟槽（204）。当晶片被加热到锡球的回流温度时发生的来自聚合物套环的暂时液化残留物（502）从聚合物套环流出。护城河是物质流动的屏障，限制了液化时残留物的扩散距离。来自聚合物套环的残留物保持在由护城河界定的区域（314）内。全深度壕沟（312）完全延伸穿过聚合物层。或者，部分深度沟槽（712和912）部分延伸穿过聚合物层。提交摘要的理解是，根据37 C.F.R，它不会用于解释或限制权利要求的范围或含义。 §1.72（b）中。

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