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1. 发明申请

WO2014209747A1 MODE DEPENDENT PARTIAL WIDTH LOAD TO WIDER REGISTER PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译：模式相关宽度负载到更大的寄存器处理器，方法和系统
公开(公告)号：WO2014209747A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/043159
申请日：2014-06-19
申请人： INTEL CORPORATION , RASH, William C. , SANTIAGO, Yazmin A. , DIXON, Martin Guy
发明人： RASH, William C. , SANTIAGO, Yazmin A. , DIXON, Martin Guy
IPC分类号： G06F9/312
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/30189 , G06F9/3836
摘要： A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates a memory location of a memory as a source operand and indicates a register as a destination operand. The method includes loading data from the indicated memory location to the processor in response to the partial width load instruction. The method includes writing at least a portion of the loaded data to a partial width of the register in response to the partial width load instruction. The method includes finishing writing the register with a set of bits stored in a remaining width of the register that have bit values that depend on a partial width load mode of the processor. The partial width load instruction does not indicate the partial width load mode. Other methods, processors, and systems are also disclosed.
摘要翻译：一种方面的方法由处理器执行。该方法包括接收部分宽度加载指令。部分宽度加载指令表示作为源操作数的存储器的存储器位置，并且将寄存器指示为目的地操作数。该方法包括响应于部分宽度加载指令将数据从指示的存储器位置加载到处理器。该方法包括响应于部分宽度加载指令将加载的数据的至少一部分写入寄存器的部分宽度。该方法包括用存储在寄存器的剩余宽度中的一组位来完成写入寄存器，该位的位值取决于处理器的部分宽度负载模式。部分宽度加载指令不表示部分宽度加载模式。还公开了其它方法，处理器和系统。

2. 发明申请

WO2013147877A1 METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM 审中-公开
标题翻译：用于处理SHA-2安全冲洗算法的方法和装置
公开(公告)号：WO2013147877A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031632
申请日：2012-03-30
申请人： INTEL CORPORATION , YAP, Kirk S. , WOLRICH, Gilbert M. , GUILFORD, James D. , GOPAL, Vinodh , OZTURK, Erdinc , GULLEY, Sean M. , FEGHALI, Wajdi K. , DIXON, Martin G.
发明人： YAP, Kirk S. , WOLRICH, Gilbert M. , GUILFORD, James D. , GOPAL, Vinodh , OZTURK, Erdinc , GULLEY, Sean M. , FEGHALI, Wajdi K. , DIXON, Martin G.
IPC分类号： H04L9/28
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
摘要翻译：处理器包括指令解码器，用于接收处理安全散列算法2（SHA-2）散列算法的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储SHA-2状态和第二操作数与第二存储位置相关联以存储多个消息和回合常数。处理器还包括执行单元，其耦合到指令解码器，以在由第一操作数和由第二操作数指定的多个消息和循环常数指定的SHA-2状态上执行SHA-2散列算法的一个或多个迭代，响应第一条指令。

3. 发明申请

WO2013101059A1 SUPERVISOR MODE EXECUTION PROTECTION 审中-公开
标题翻译：监督模式执行保护
公开(公告)号：WO2013101059A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067838
申请日：2011-12-29
申请人： INTEL CORPORATION , VAN DE VEN, Adriaan , PATEL, Baiju, V. , MALLICK, Asit, K. , NEIGER, Gilbert , COKE, James, S. , DIXON, Martin, G. , BRANDT, Jason, W.
发明人： VAN DE VEN, Adriaan , PATEL, Baiju, V. , MALLICK, Asit, K. , NEIGER, Gilbert , COKE, James, S. , DIXON, Martin, G. , BRANDT, Jason, W.
IPC分类号： G06F21/22 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/30043 , G06F12/0292 , G06F12/1009 , G06F12/1491
摘要： Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.
摘要翻译：公开了用于监督模式执行保护的装置和方法。在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。存储器中的区域是用户存储器。执行硬件是执行指令。当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

4. 发明申请

WO2013095576A1 PROCESSOR-BASED APPARATUS AND METHOD FOR PROCESSING BIT STREAMS 审中-公开
标题翻译：基于处理器的设备和处理位流的方法
公开(公告)号：WO2013095576A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067036
申请日：2011-12-22
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , OZTURK, Erdinc , FEGHALI, Wajdi K. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G. , CHAPPELL, Robert S.
发明人： GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , OZTURK, Erdinc , FEGHALI, Wajdi K. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G. , CHAPPELL, Robert S.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/34
摘要： An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.
摘要翻译：描述了一种用于使用面向位的指令来处理比特流的装置和方法。例如，根据一个实施例的方法包括以下操作：执行用于获得用于操作的比特的指令，所述指令标识起始比特地址和要检索的比特数; 从面向比特的寄存器或高速缓存中检索由起始位地址和位数标识的位; 并对所检索的位执行指定位操作的序列以产生结果。

5. 发明申请

WO2013095504A1 MATRIX MULTIPLY ACCUMULATE INSTRUCTION 审中-公开
标题翻译：矩阵多项累积指令
公开(公告)号：WO2013095504A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066814
申请日：2011-12-22
申请人： INTEL CORPORATION , GOPAL, Vinodh , WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GULLEY, Sean M. , FEGHALI, Wajdi K. , DIXON, Martin G.
发明人： GOPAL, Vinodh , WOLRICH, Gilbert M. , YAP, Kirk S. , GUILFORD, James D. , OZTURK, Erdinc , GULLEY, Sean M. , FEGHALI, Wajdi K. , DIXON, Martin G.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： H04L9/0631 , G06F9/30007 , G06F9/3001 , G06F9/30036 , H04L9/0643
摘要： A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.
摘要翻译：描述了一种方法。该方法包括对存储在第三寄存器中的结果矩阵中的每个位置迭代执行，将存储在第一寄存器中的矩阵位置处的值乘以存储在第二寄存器中的矩阵位置处的值，以获得第一乘法值，其中第一寄存器和第二寄存器中的位置由结果矩阵中的位置确定，并且执行具有第一乘法值的异或（XOR）操作和存储在存储在第三寄存器中的结果矩阵位置处的值以获得结果值。

6. 发明申请

WO2013095484A1 INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING 审中-公开
标题翻译：执行JH CRYPTOGRAPHIC HASHING的指示
公开(公告)号：WO2013095484A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066733
申请日：2011-12-22
申请人： INTEL CORPORATION , YAP, Kirk S. , WOLRICH, Gilbert M. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , GULLEY, Sean M. , FEGHALI, Wajdi K. , DIXON, Martin G.
发明人： YAP, Kirk S. , WOLRICH, Gilbert M. , GOPAL, Vinodh , GUILFORD, James D. , OZTURK, Erdinc , GULLEY, Sean M. , FEGHALI, Wajdi K. , DIXON, Martin G.
IPC分类号： H04L9/28 , H04L9/12
CPC分类号： G06F21/64 , H04L9/0643 , H04L2209/12
摘要： A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed
摘要翻译：描述了一种方法。该方法包括在JH状态下执行一个或多个JH_SBOX_L指令来执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换

7. 发明申请

WO2011087589A3 SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES 审中-公开
标题翻译：系统，方法和装置，用于高速缓存页面和TLB无效的入口范围
公开(公告)号：WO2011087589A3
公开(公告)日：2011-10-27
申请号：PCT/US2010058236
申请日：2010-11-29
申请人： INTEL CORP , DIXON MARTIN G , RODGERS SCOTT D
发明人： DIXON MARTIN G , RODGERS SCOTT D
IPC分类号： G06F12/08 , G06F9/312
CPC分类号： G06F12/1009 , G06F12/0891 , G06F12/1027 , G06F2212/1016
摘要： Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.
摘要翻译：描述了用于执行多个高速缓存行的刷新和/或多个翻译后备缓冲器（TLB）条目的无效的系统，方法和装置。在一种这样的方法中，为了冲洗处理器的多个高速缓存行，包括指示处理器的多个高速缓存行将被刷新的第一字段的单个指令并且响应于单个指令，刷新多个高速缓存处理器的行。

8. 发明申请

WO2011087558A2 CONTROLLING TIME STAMP COUNTER (TSC) OFFSETS FOR MULITPLE CORES AND THREADS 审中-公开
标题翻译：控制时间戳计数器（TSC）偏移多个核心和线程
公开(公告)号：WO2011087558A2
公开(公告)日：2011-07-21
申请号：PCT/US2010056165
申请日：2010-11-10
申请人： INTEL CORP , DIXON MARTIN , SHRALL JEREMY J , PARTHASARATHY RAJESH S
发明人： DIXON MARTIN , SHRALL JEREMY J , PARTHASARATHY RAJESH S
CPC分类号： G06F1/14 , G06F11/1658
摘要： In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在系统暂停之前记录处理器的第一TSC计数器的时间戳计数器（TSC）值，在系统暂停之后访问所存储的TSC值并直接更新线程偏移值与在处理器的第一核上执行的具有所存储的TSC值的第一线程相关联，而不执行处理器的多个核之间的同步。描述并要求保护其他实施例。

9. 发明申请

WO2011075246A2 INSTRUCTION FOR ENABLING A PROCESSOR WAIT STATE 审中-公开
标题翻译：启动处理器等待状态的指令
公开(公告)号：WO2011075246A2
公开(公告)日：2011-06-23
申请号：PCT/US2010056320
申请日：2010-11-11
申请人： INTEL CORP , DIXON MARTIN G , RODGERS SCOTT D , GUNTHER STEPHEN H , SETHI PRASHANT , BAHRAMI TARANEH , HAMMARLUND PER
发明人： DIXON MARTIN G , RODGERS SCOTT D , GUNTHER STEPHEN H , SETHI PRASHANT , BAHRAMI TARANEH , HAMMARLUND PER
IPC分类号： G06F9/30 , G06F1/32 , G06F9/46
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3293 , G06F9/30083 , G06F9/3009 , Y02D10/122 , Y02D50/20
摘要： In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于定时器值。处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。描述和要求保护其他实施例。

10. 发明申请

WO2013095547A9 APPARATUS AND METHOD OF EXECUTION UNIT FOR CALCULATING MULTIPLE ROUNDS OF A SKEIN HASHING ALGORITHM 审中-公开
标题翻译：用于计算多重环绕滑移算法的执行单元的装置和方法
公开(公告)号：WO2013095547A9
公开(公告)日：2013-09-06
申请号：PCT/US2011066988
申请日：2011-12-22
申请人： INTEL CORP , WOLRICH GILBERT M , YAP KIRK S , GUILFORD JAMES D , OZTURK ERDINC , GOPAL VINODH , FEGHALI WAJDI K , GULLEY SEAN M , DIXON MARTIN G
发明人： WOLRICH GILBERT M , YAP KIRK S , GUILFORD JAMES D , OZTURK ERDINC , GOPAL VINODH , FEGHALI WAJDI K , GULLEY SEAN M , DIXON MARTIN G
IPC分类号： G06F1/00 , G06F9/305 , G06F9/44
CPC分类号： G06F9/30029 , G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/3885 , G06F9/3895 , H04L9/0643
摘要： An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
摘要翻译：描述了包括指令流水线内的执行单元的装置。执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

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