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1. 发明申请

WO2007020264B1 SYSTEM AND METHOD FOR LIMITING THE SIZE OF A LOCAL STORAGE OF A PROCESSOR 审中-公开
标题翻译：用于限制处理器的本地存储器大小的系统和方法
公开(公告)号：WO2007020264B1
公开(公告)日：2007-10-11
申请号：PCT/EP2006065326
申请日：2006-08-15
申请人： IBM , IBM UK , BURNS ADAM PATRICK , DAY MICHAEL NORMAN , FLACHS BRIAN , HOFSTEE HARM PETER , JOHNS CHARLES RAY , LIBERTY JOHN SAMUEL
发明人： BURNS ADAM PATRICK , DAY MICHAEL NORMAN , FLACHS BRIAN , HOFSTEE HARM PETER , JOHNS CHARLES RAY , LIBERTY JOHN SAMUEL
IPC分类号： G06F12/06
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统和方法。提供与处理器相关联的设施以设置本地存储大小限制。该设施是一个特权设施，只能通过在多处理器系统中的控制处理器上运行的操作系统或相关处理器本身访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模是用于访问本地存储。

2. 发明申请

WO2007045657A1 DESTRUCTIVE DMA LISTS 审中-公开
标题翻译：破坏性DMA列表
公开(公告)号：WO2007045657A1
公开(公告)日：2007-04-26
申请号：PCT/EP2006/067508
申请日：2006-10-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , DAY, Michael, Norman , JOHNS, Charles, Ray , MINOR, Barry
发明人： DAY, Michael, Norman , JOHNS, Charles, Ray , MINOR, Barry
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destroy the DMA list and the extra storage space for the DMA list is saved.
摘要翻译：提供了用于DMA传输的缓冲器，方法和计算机程序产品，其被设计为在处理器的本地存储器内节省存储器空间。缓冲区是具有为DMA列表保留的部分的返回缓冲区。 DMA控制器通过以下方式完成DMA传输：从位于DMA列表部分的DMA列表读取地址元素; 从系统内存读取相应的数据; 并将相应的数据复制到返回缓冲器部分。此缓冲区可节省空间，因为当缓冲区开始填满相应的返回数据时，可以覆盖DMA列表中的数据。因此，DMA列表覆盖在返回缓冲器的顶部，使得返回数据可以破坏DMA列表，并且保存DMA列表的额外的存储空间。

3. 发明申请

WO2006034931A1 SYSTEM AND METHOD FOR VIRTUALIZATION OF PROCESSOR RESOURCES 审中-公开
标题翻译：用于处理器资源虚拟化的系统和方法
公开(公告)号：WO2006034931A1
公开(公告)日：2006-04-06
申请号：PCT/EP2005/054164
申请日：2005-08-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , AGUILAR, Maximino, Jr. , DAY, Michael, Norman , NUTTER, Mark, Richard , XENIDIS, James
发明人： AGUILAR, Maximino, Jr. , DAY, Michael, Norman , NUTTER, Mark, Richard , XENIDIS, James
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1045
摘要： In a system and method for virtualization of processor resources, a thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a "soft" copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.
摘要翻译：在用于处理器资源的虚拟化的系统和方法中，在处理器上创建线程，并且将处理器的本地存储器映射到有效的地址空间中。这样做，处理器的本地内存可以由其他处理器访问，无论处理器是否正在运行。附加线程会在有效地址空间中创建额外的本地内存映射。有效地址空间对应于物理本地存储器或“软”复制区域。当处理器运行时，不同的处理器可以从处理器的本地存储区域访问位于第一处理器的本地存储器中的数据。当处理器未运行时，处理器的本地存储器的软拷贝存储在其他处理器的存储器位置（即锁定的高速缓冲存储器，固定的系统存储器，虚拟存储器等）中以继续访问。

4. 发明申请

WO2008012159A1 LOGICAL PARTITIONING AND VIRTUALIZATION IN A HETEROGENEOUS ARCHITECTURE 审中-公开
标题翻译：异构建筑中的逻辑分区和虚拟化
公开(公告)号：WO2008012159A1
公开(公告)日：2008-01-31
申请号：PCT/EP2007/056412
申请日：2007-06-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , DAY, Michael, Norman , GSCHWIND, Michael, Karl , NUTTER, Mark, Richard , XENIDIS, James
发明人： DAY, Michael, Norman , GSCHWIND, Michael, Karl , NUTTER, Mark, Richard , XENIDIS, James
IPC分类号： G06F9/50
CPC分类号： G06F9/5077
摘要： A method, apparatus, and computer usable program code for logical partitioning and virtualization in heterogeneous computer architecture. In one illustrative embodiment, a portion of a first set of processors of a first type is allocated to a partition in a heterogeneous logically partit ioned system and a portion of a second set of processors of a second type is allocated to the partition.
摘要翻译：用于异构计算机体系结构中逻辑分区和虚拟化的方法，设备和计算机可用程序代码。在一个说明性实施例中，第一类型的第一组处理器的一部分被分配给异构逻辑分离离子系统中的分区，并且第二类型的第二组处理器的一部分被分配给分区。

5. 发明申请

WO2007020274A3 SYSTEM AND METHOD FOR COMMUNICATING INSTRUCTIONS AND DATA BETWEEN A PROCESSOR AND EXTERNAL DEVICES 审中-公开
标题翻译：用于通信处理器和外部设备之间的指令和数据的系统和方法
公开(公告)号：WO2007020274A3
公开(公告)日：2007-04-19
申请号：PCT/EP2006065372
申请日：2006-08-16
申请人： IBM , IBM UK , DAY MICHAEL NORMAN , JOHNS CHARLES RAY , LIBERTY JOHN SAMUEL , SWANSON TODD , TRUONG THUONG QUANG
发明人： DAY MICHAEL NORMAN , JOHNS CHARLES RAY , LIBERTY JOHN SAMUEL , SWANSON TODD , TRUONG THUONG QUANG
IPC分类号： G06F13/28 , G06F15/163 , H04Q3/545
CPC分类号： G06F13/28
摘要： A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power "stall" state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和外部设备之间传送指令和数据的系统和方法。系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或者没有可用空间来写入对应的寄存器时，处理器处于低功率“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

6. 发明申请

WO2007020264A1 SYSTEM AND METHOD FOR LIMITING THE SIZE OF A LOCAL STORAGE OF A PROCESSOR 审中-公开
标题翻译：限制处理器的本地存储大小的系统和方法
公开(公告)号：WO2007020264A1
公开(公告)日：2007-02-22
申请号：PCT/EP2006/065326
申请日：2006-08-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BURNS, Adam Patrick , DAY, Michael Norman , FLACHS, Brian , HOFSTEE, Harm Peter , JOHNS, Charles Ray , LIBERTY, John Samuel
发明人： BURNS, Adam Patrick , DAY, Michael Norman , FLACHS, Brian , HOFSTEE, Harm Peter , JOHNS, Charles Ray , LIBERTY, John Samuel
IPC分类号： G06F12/06
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统和方法。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

7. 发明申请

WO2006021473A1 MESSAGE DELIVERY ACROSS A PLURALITY OF PROCESSORS 审中-公开
标题翻译：消息传递交给多个处理器
公开(公告)号：WO2006021473A1
公开(公告)日：2006-03-02
申请号：PCT/EP2005/053542
申请日：2005-07-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , AGUILAR, Maximino , DAY, Michael, Norman , NUTTER, Mark, Richard , STAFFORD, James, Michael
发明人： AGUILAR, Maximino , DAY, Michael, Norman , NUTTER, Mark, Richard , STAFFORD, James, Michael
IPC分类号： G06F9/46
CPC分类号： G06F9/4812 , G06F9/52
摘要： A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor decodes an interrupt and determines which support processor generated the interrupt. The main processor then determines whether a kernel or an application should process the interrupt. Interrupts such as page faults, segment faults, and alignment errors are handled by the kernel, while "informational" signals, such as stop and signal requests, halt requests, mailbox requests, and DMC tag complete requests are handled by the application. In addition, multiple identical events are maintained, and event data may be included in the interrupt using the invention described herein.
摘要翻译：提供了一种系统和方法，用于将消息传递到在多处理环境中操作的处理器。在多处理器环境中，通过将事件存储在与特定支持处理器对应的队列中来管理中断。主处理器解码中断并确定哪个支持处理器产生中断。然后，主处理器确定内核或应用程序是否应该处理中断。内核处理诸如页面错误，段错误和对齐错误等中断，应用程序会处理“信息”信号，如停止和信号请求，暂停请求，邮箱请求和DMC标签完成请求。另外，维护多个相同的事件，并且可以使用本文所述的发明将事件数据包括在中断中。

8. 发明申请

WO2007020274A2 SYSTEM AND METHOD FOR COMMUNICATING INSTRUCTIONS AND DATA BETWEEN A PROCESSOR AND EXTERNAL DEVICES 审中-公开
标题翻译：用于在处理器和外部设备之间传送指令和数据的系统和方法
公开(公告)号：WO2007020274A2
公开(公告)日：2007-02-22
申请号：PCT/EP2006/065372
申请日：2006-08-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , DAY, Michael, Norman , JOHNS, Charles, Ray , LIBERTY, John, Samuel , SWANSON, Todd , TRUONG, Thuong, Quang
发明人： DAY, Michael, Norman , JOHNS, Charles, Ray , LIBERTY, John, Samuel , SWANSON, Todd , TRUONG, Thuong, Quang
IPC分类号： H04Q3/545 , G06F13/16
CPC分类号： G06F13/28
摘要： A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power "stall" state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了用于在处理器和外部设备之间传送指令和数据的系统和方法。该系统和方法利用通道接口作为处理器和存储器流量控制器之间通信的主要机制。例如，通道接口提供了与处理器设施，存储器流量控制设施，机器状态寄存器和外部处理器中断设施进行通信的通道。这些频道可以被指定为阻止或非阻止。对于阻塞通道，当没有数据可用于从对应寄存器读取时，或者没有空间可用于写入相应寄存器时，处理器被置于低功率“失速”状态。州。当数据可用或释放空间时，处理器会自动唤醒，通过阻塞通道进行通信。因此，本发明的信道允许处理器保持在低功率状态。

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