专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012003275A1 PARALLEL USE OF INTEGRATED NON-VOLATILE MEMORY AND MAIN VOLATILE MEMORY WITHIN A MOBILE DEVICE 审中-公开
标题翻译：在移动设备中并行使用集成的非易失性存储器和主要的易失性存储器
公开(公告)号：WO2012003275A1
公开(公告)日：2012-01-05
申请号：PCT/US2011/042526
申请日：2011-06-30
申请人： QUALCOMM Incorporated , CHUN, Christopher Kong Yee
发明人： CHUN, Christopher Kong Yee
IPC分类号： G06F12/02 , G06F12/06 , G06F11/14
CPC分类号： G06F12/0223 , G06F11/1441 , G06F11/1456 , G06F12/0638 , Y02D10/13
摘要： A mobile device having parallel use of non-volatile memory and main memory is presented. The mobile device includes a volatile memory, a non volatile memory, a memory controller functionally coupled to the non-volatile memory and the volatile memory, and a processor coupled to the memory controller. The processor addresses both the non-volatile memory and the volatile memory utilizing a continuous memory map. Alternatively, a mobile device may include a volatile memory, a non-volatile memory, a memory controller coupled to the volatile memory, a processor coupled to the memory controller. The processor may address the volatile memory during normal operation. The mobile device may further include a shadow copy controller coupled to the non-volatile memory and the memory controller, where the shadow copy controller copies information stored in a designated portion of the volatile memory into the non-volatile memory.
摘要翻译：提出了具有并行使用非易失性存储器和主存储器的移动设备。移动设备包括易失性存储器，非易失性存储器，功能上耦合到非易失性存储器和易失性存储器的存储器控制器，以及耦合到存储器控制器的处理器。处理器利用连续存储器映射来寻址非易失性存储器和易失性存储器。或者，移动设备可以包括易失性存储器，非易失性存储器，耦合到易失性存储器的存储器控制器，耦合到存储器控制器的处理器。处理器可以在正常操作期间寻址易失性存储器。移动设备还可以包括耦合到非易失性存储器和存储器控制器的卷影复制控制器，其中卷影复制控制器将存储在易失性存储器的指定部分中的信息复制到非易失性存储器中。

2. 发明申请

WO2011085323A3 SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME 审中-公开
公开(公告)号：WO2011085323A3
公开(公告)日：2011-07-14
申请号：PCT/US2011/020701
申请日：2011-01-10
申请人： QUALCOMM INCORPORATED , THOMSON, Steven S. , IRANLI, Ali , DROP, Michael J. , CUPPU, Vinodh R. , CHUN, Christopher Kong Yee , XUE, Tao , LO, Haw-Jing , KHAN, Moinul, H.
发明人： THOMSON, Steven S. , IRANLI, Ali , DROP, Michael J. , CUPPU, Vinodh R. , CHUN, Christopher Kong Yee , XUE, Tao , LO, Haw-Jing , KHAN, Moinul, H.
IPC分类号： G06F1/32
摘要： A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

3. 发明申请

WO2011085323A2 SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME 审中-公开
标题翻译：实时监控中央处理单元的系统及方法
公开(公告)号：WO2011085323A2
公开(公告)日：2011-07-14
申请号：PCT/US2011020701
申请日：2011-01-10
申请人： QUALCOMM INC , THOMSON STEVEN S , IRANLI ALI , DROP MICHAEL J , CUPPU VINODH R , CHUN CHRISTOPHER KONG YEE , XUE TAO , LO HAW-JING , KHAN MOINUL H
发明人： THOMSON STEVEN S , IRANLI ALI , DROP MICHAEL J , CUPPU VINODH R , CHUN CHRISTOPHER KONG YEE , XUE TAO , LO HAW-JING , KHAN MOINUL H
IPC分类号： G06F9/00 , G06F13/24
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.
摘要翻译：公开了实时监控一个或多个中央处理单元的方法。该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。

4. 发明申请

WO2012006048A1 SURROGATE CIRCUIT FOR TESTING AN INTERFACE 审中-公开
标题翻译：用于测试接口的电流检测电路
公开(公告)号：WO2012006048A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/042089
申请日：2011-06-28
申请人： QUALCOMM INCORPORATED , CHUN, Christopher, Kong, Yee , SRINIVASAN, Anand
发明人： CHUN, Christopher, Kong, Yee , SRINIVASAN, Anand
IPC分类号： G06F11/26
CPC分类号： G06F11/261 , G06F11/221
摘要： A semiconductor die includes interface logic for performing a function on an external device, and a surrogate circuit in communication with the interface logic. The surrogate circuit has a similar operation to that of the external circuit, and the interface logic facilitates testing of the interface logic by attempting to perform the function on the surrogate circuit. The interface logic may be a memory interface, and the surrogate circuit may be a memory circuit that is a smaller and simpler replica of an external memory die. The surrogate circuit allows the interface logic to be tested before the semiconductor die is physically coupled to the external device, for exampled in a three dimensional ( 3D) integrated circuit (IC).
摘要翻译：半导体管芯包括用于在外部设备上执行功能的接口逻辑和与接口逻辑通信的代理电路。替代电路具有与外部电路类似的操作，并且接口逻辑有助于通过尝试执行代理电路上的功能来测试接口逻辑。接口逻辑可以是存储器接口，并且代理电路可以是作为外部存储器管芯的更小和更简单的副本的存储器电路。替代电路允许在半导体管芯物理耦合到外部器件之前测试接口逻辑，以便在三维（3D）集成电路（IC）中进行示例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式