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1. 发明申请

WO2012059121A1 MEMORY ARRANGEMENT FOR ACCESSING MATRICES 审中-公开
标题翻译：用于访问矩阵的内存安排
公开(公告)号：WO2012059121A1
公开(公告)日：2012-05-10
申请号：PCT/EP2010/066567
申请日：2010-11-01
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , CATOVIC, Edvin , SIHLBOM, Björn Ulf Anders
发明人： CATOVIC, Edvin , SIHLBOM, Björn Ulf Anders
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0207 , G06F12/0607 , G11C8/06 , G11C8/12
摘要： A method and memory arrangement (1, 2) and is provided having a plurality of memory elements (3), the elements being associated with a memory space (20) which can be addressed in a row and column fashion during a write or a read access, the memory arrangement comprising a first macro bank (MB0) comprising a first plurality of memory cells (RCO - RC3), the first plurality of memory cells comprising a first subset of the memory elements (3): a second macro bank (MB1) comprising a second plurality of memory cells, the second plurality of memory cells comprising a second subset of the memory elements (3); an address resolution stage (11) for addressing the memory cells (RCO - RC3) in the respective macro banks (MB0, MB1). The memory cells (p) are arranged so that the memory space (20) is partitioned into a plurality of non-overlapping basic matrices (10); whereby each basic matrix (10) is mapped to a given macro bank (MB1 - MB3) and wherein the memory cells (p) are arranged logically so that the memory space (20) is partitioned into a plurality of non-overlapping logic matrices (30) of a given size (S), each logic matrix (30) being of a size equal or larger than a basic (10) matrix. The address resolution stage (11) is adapted for transforming a logic address (R, C, r, c, d, S) as designating the location of the memory element (3) in the logic matrix (r, c) and the location of the logic matrix in the memory space (R, C) and a direction (d) indicating either row or column access of the memory space and the size (S) of the logic matrix into a resolved address (A), the memory arrangement further comprising algorithm functions (12, 13) which transform the resolved address into a set of macro bank addresses (A 0 ; A 1 ), which by each macro bank (MB0 - MB3) again are transformed into a plurality of memory cell addresses (A 00 , A 01 ; A 02 , and A 03 ); the memory cell addresses pointing out elements (3) of given memory cells of each macro bank.
摘要翻译：一种方法和存储器装置（1,2），并且被提供有多个存储元件（3），所述元件与存储器空间（20）相关联，所述存储器空间（20）可以在写入或读取期间以行和列方式寻址所述存储器装置包括包括第一多个存储单元（RCO-RC3）的第一宏块（MB0），所述第一多个存储单元包括所述存储元件（3）的第一子集：第二宏组（MB1 ）包括第二多个存储器单元，所述第二多个存储器单元包括所述存储器元件（3）的第二子集; 用于寻址各个宏组（MB0，MB1）中的存储单元（RCO-RC3）的地址解析级（11）。存储单元（p）被布置成使得存储器空间（20）被划分成多个非重叠的基本矩阵（10）; 由此将每个基本矩阵（10）映射到给定宏组（MB1-MB3），并且其中存储单元（p）被逻辑地布置，使得存储器空间（20）被划分成多个不重叠的逻辑矩阵 30），每个逻辑矩阵（30）的尺寸等于或大于基本（10）矩阵。地址解析级（11）适于将逻辑地址（R，C，r，c，d，S）变换为指定逻辑矩阵（r，c）中的存储元件（3）的位置和位置存储器空间（R，C）中的逻辑矩阵和指示存储器空间的行或列存取的方向（d）和逻辑矩阵的大小（S）分解成解析地址（A）的存储器装置还包括将分辨后的地址变换成宏组地址（A0; A1）的集合的算法函数（12,13），由宏组（MB0-MB3）再次变换为多个存储单元地址（A00， A01; A02和A03）; 存储单元地址指出每个宏组的给定存储单元的元素（3）。

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