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1. 发明申请

WO2010013196A2 A METHOD TO LINEARIZE THE OUTPUT FROM AN ADC 审中-公开
标题翻译：线性化来自ADC的输出的方法
公开(公告)号：WO2010013196A2
公开(公告)日：2010-02-04
申请号：PCT/IB2009/053273
申请日：2009-07-28
申请人： NXP B.V. , HEKSTRA,, Andries Pieter , BREEMS, Lucien Johannes , RUTTEN, Robert
发明人： HEKSTRA,, Andries Pieter , BREEMS, Lucien Johannes , RUTTEN, Robert
CPC分类号： H03M3/386 , H03M3/43 , H03M3/456
摘要： A method is disclosed of compensating the output of an ADC for non- linearity in the response of the ADC. The methodcomprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.
摘要翻译：公开了一种在ADC的响应中补偿ADC的输出以实现非线性的方法。该方法包括将模拟输入信号转换为未校正的数字ADC输出采样，将校正变量的矢量应用于未校正的ADC输出采样块中的每一个，以提供经校正的ADC采样块，以及迭代地最小化经校正的ADC采样块与对校正变量向量的响应。

2. 发明申请

WO2010113108A1 FREQUENCY SYNTHESISER 审中-公开
标题翻译：频率合成器
公开(公告)号：WO2010113108A1
公开(公告)日：2010-10-07
申请号：PCT/IB2010/051371
申请日：2010-03-30
申请人： NXP B.V. , DRAGO, Salvatore , SEBASTIANO, Fabio , LEENAERTS, Dominicus, Martinus, Wilhelmus , BREEMS, Lucien, Johannes , NAUTA, Bram
发明人： DRAGO, Salvatore , SEBASTIANO, Fabio , LEENAERTS, Dominicus, Martinus, Wilhelmus , BREEMS, Lucien, Johannes , NAUTA, Bram
IPC分类号： H03K3/03 , H03L7/08 , H03L7/099
CPC分类号： H03K3/0322 , H03K3/012 , H03L7/0802 , H03L7/087 , H03L7/0995 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A low power frequency synthesiser circuit (30) for a radio transceiver, the synthesiser circuit comprising: a digital controlled oscillator (33) configured to generate an output signal (F 0 ) having a frequency controlled by an input digital control word (DCW); a feedback loop (35-38) connected between an output and an input of the digital controlled oscillator, the feedback loop configured to provide the digital control word to the input of the digital controlled oscillator from an error derived from an input frequency control word (FCW) and the output signal; and a duty cycle module (32) connected to the digital controlled oscillator and the feedback loop, the duty cycle module configured to generate a plurality of control signals to periodically enable and disable the digital controlled oscillator for a set fraction of clock cycles of an input reference clock signal (RefClock).
摘要翻译：一种用于无线电收发器的低功率频率合成器电路（30），所述合成器电路包括：数字控制振荡器（33），被配置为产生具有由输入数字控制字（DCW）控制的频率的输出信号（F0）; 连接在数字控制振荡器的输出和输入端之间的反馈回路（35-38），所述反馈回路被配置成从数字控制振荡器的输入端向从数字控制振荡器的输入提供数字控制字 FCW）和输出信号; 以及连接到数字控制振荡器和反馈回路的占空比模块（32），所述占空比模块被配置为产生多个控制信号，以周期性地启用和禁用数字控制振荡器用于输入的时钟周期的一小部分参考时钟信号（RefClock）。

3. 发明申请

WO2009040697A3 AUTOMATIC COMMON-MODE REJECTION CALIBRATION 审中-公开
公开(公告)号：WO2009040697A3
公开(公告)日：2009-04-02
申请号：PCT/IB2008/053723
申请日：2008-09-15
申请人： NXP B.V. , SEBASTIANO, Fabio , BREEMS, Lucien, Johannes , ROOVERS, Raf, Lodewijk, Jan
发明人： SEBASTIANO, Fabio , BREEMS, Lucien, Johannes , ROOVERS, Raf, Lodewijk, Jan
IPC分类号： H03F1/30 , H03F3/45
摘要： The present invention relates to a circuit and a method for automatic common- mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection. The circuit for automatic common-mode rejection calibration in a differential conversion system comprises an analog input stage for an analog input signal (101), an analog-digital-converter (106) for converting an analog signal (107) into its digital representation (108), a digital block (105) arranged to adapt said digital representation (108) of a portion of a DC offset of said analog input signal (101) in accordance with whether said analog input signal (101) is in a predetermined input range of said analog-digital-converter (106), and a digital-analog-converter (103) arranged in a feedback path (102) from said digital block (105) to subtraction means (111) of said analog input stage for converting a digital signal (104) into an analog output signal (109), wherein said analog output signal (109) is subtracted from said analog input signal (101) resulting in said analog signal (107).

4. 发明申请

WO2010046859A1 SIGMA-DELTA MODULATOR 审中-公开
标题翻译： SIGMA-DELTA调制器
公开(公告)号：WO2010046859A1
公开(公告)日：2010-04-29
申请号：PCT/IB2009/054643
申请日：2009-10-21
申请人： NXP B.V. , VAN VELDHOVEN, Robert Henrikus Margaretha , BREEMS, Lucien Johannes , RUTTEN, Robert
发明人： VAN VELDHOVEN, Robert Henrikus Margaretha , BREEMS, Lucien Johannes , RUTTEN, Robert
IPC分类号： H03M3/00 , H03M1/06
CPC分类号： H03M3/368 , H03M3/436
摘要： A sigma-delta modulator (400) 400, 500, 600) for converting an input signal (X(s)) (X(s)) to a quantized output signal (Y(z)) (Y(z)), in which a feedback loop is provided between a filter (402) and a quantizer (403) of the modulator, the feedback loop configured to reduce quantization errors from the modulator by filtering and subtracting quantization noise fed back to an input of the quantizer (403).
摘要翻译：用于将输入信号（X（s））（X（s））转换为量化输出信号（Y（z））（Y（z））的Σ-Δ调制器（400）400,500,600）在调制器的滤波器（402）和量化器（403）之间提供反馈回路，反馈回路经配置以通过滤波和减去反馈给量化器（403）的输入的量化噪声来减少来自调制器的量化误差，。

5. 发明申请

WO2009044365A3 METHOD AND SYSTEM FOR IMPULSE RADIO WAKEUP 审中-公开
公开(公告)号：WO2009044365A3
公开(公告)日：2009-04-09
申请号：PCT/IB2008/054037
申请日：2008-10-02
申请人： NXP B.V. , SEBASTIANO, Fabio , DRAGO, Salvatore , BREEMS, Lucien, Johannes , LEENAERTS, Dominicus, Martinus, Wilhelmus
发明人： SEBASTIANO, Fabio , DRAGO, Salvatore , BREEMS, Lucien, Johannes , LEENAERTS, Dominicus, Martinus, Wilhelmus
IPC分类号： H04B1/16
摘要： Communication networks are implemented using a variety of devices and methods. In a particular embodiment for use in a communication network having RF- communication devices that communicate using a RF protocol, an RF-communication device is implemented with an RF transceiver (110) to communicate over the network using the RF protocol and being controllable in a reduced power-consumption mode in which the RF transceiver does not communicate over the network. The device also includes an RF receiver (104, 106) including an envelope detector (104) and a pulse generator circuit (106). The envelope detector circuit (104) providing an envelope-based signal to a pulse generator circuit (106) that, in response to the envelope-based signal and after generating a number of pulses that exceeds a predetermined number of pulses, prompts the RF transceiver (110) to transition out of the reduced power-consumption mode.

6. 发明申请

WO2009044365A2 METHOD AND SYSTEM FOR IMPULSE RADIO WAKEUP 审中-公开
标题翻译：用于脉冲无线电唤醒的方法和系统
公开(公告)号：WO2009044365A2
公开(公告)日：2009-04-09
申请号：PCT/IB2008054037
申请日：2008-10-02
申请人： NXP BV , SEBASTIANO FABIO , DRAGO SALVATORE , BREEMS LUCIEN JOHANNES , LEENAERTS DOMINICUS MARTINUS WILHELMUS
发明人： SEBASTIANO FABIO , DRAGO SALVATORE , BREEMS LUCIEN JOHANNES , LEENAERTS DOMINICUS MARTINUS WILHELMUS
IPC分类号： H04B1/16
CPC分类号： H04W52/0229 , Y02D70/00
摘要： Communication networks are implemented using a variety of devices and methods. In a particular embodiment for use in a communication network having RF- communication devices that communicate using a RF protocol, an RF-communication device is implemented with an RF transceiver (110) to communicate over the network using the RF protocol and being controllable in a reduced power-consumption mode in which the RF transceiver does not communicate over the network. The device also includes an RF receiver (104, 106) including an envelope detector (104) and a pulse generator circuit (106). The envelope detector circuit (104) providing an envelope-based signal to a pulse generator circuit (106) that, in response to the envelope-based signal and after generating a number of pulses that exceeds a predetermined number of pulses, prompts the RF transceiver (110) to transition out of the reduced power-consumption mode.
摘要翻译：通信网络使用各种设备和方法来实现。在用于具有使用RF协议进行通信的RF通信设备的通信网络中的特定实施例中，RF通信设备与RF收发器（110）一起实现以使用RF协议通过网络进行通信并且可在降低功耗模式，其中RF收发器不通过网络进行通信。该设备还包括包括包络检测器（104）和脉冲发生器电路（106）的RF接收器（104,106）。包络检测器电路（104）向脉冲发生器电路（106）提供基于包络的信号，该脉冲发生器电路（106）响应于基于包络的信号并且在产生超过预定数量的脉冲的脉冲数之后，提示RF收发器（110）从所述降低功耗模式转换出来。

7. 发明申请

WO2006043207A1 SIGNAL RECEIVER AND MOBILE COMMUNICATION DEVICE 审中-公开
标题翻译：信号接收机和移动通信设备
公开(公告)号：WO2006043207A1
公开(公告)日：2006-04-27
申请号：PCT/IB2005/053344
申请日：2005-10-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN VELDHOVEN, Robert, Henrikus, Margaretha , BREEMS, Lucien, Johannes
发明人： VAN VELDHOVEN, Robert, Henrikus, Margaretha , BREEMS, Lucien, Johannes
IPC分类号： H03M3/04
CPC分类号： H03M3/394 , H03M3/424 , H03M3/452 , H03M3/462
摘要： A signal receiver processing circuit is for isolating a desired signal from analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) and an analog to digital converter (14) for providing a digital signal to a digital signal processor (15), the digital signal processor including a digital filter. The device has a control unit (16) for adjusting a filtering accuracy of the analog to digital converter (14) and/or the digital signal processor unit (15) in dependence of a signal quality of the input signal.
摘要翻译：信号接收机处理电路用于将期望的信号与容易受信号功率变化影响的模拟输入信号进行隔离。从无线电前端（12）。该装置具有可变增益放大器（13）和用于向数字信号处理器（15）提供数字信号的模数转换器（14），数字信号处理器包括数字滤波器。该装置具有控制单元（16），用于根据输入信号的信号质量来调节模数转换器（14）和/或数字信号处理器单元（15）的滤波精度。

8. 发明申请

WO2010046853A3 SIGMA-DELTA MODULATOR 审中-公开
标题翻译： SIGMA-DELTA调制器
公开(公告)号：WO2010046853A3
公开(公告)日：2010-08-19
申请号：PCT/IB2009054632
申请日：2009-10-21
申请人： NXP BV , BREEMS LUCIEN JOHANNES , VAN VELDHOVEN ROBERT HENRIKUS MARGARETHA , RUTTEN ROBERT
发明人： BREEMS LUCIEN JOHANNES , VAN VELDHOVEN ROBERT HENRIKUS MARGARETHA , RUTTEN ROBERT
IPC分类号： H03M3/02
CPC分类号： H03M3/414
摘要： A cascaded sigma-delta analog to digital converter (300) comprising a first sigma-delta modulator (310) having an input configured to receive an input signal, a second sigma-delta modulator (320) configured to receive an error signal from the first modulator and a noise filter (230) configured to receive an output signal from each of the first and second modulators and to provide a modulated and filtered output signal, wherein the analog to digital converter comprises an adder (216) configured to provide the error signal from the first modulator by combining an output signal from a loop filter (212) of the first modulator with the input signal.
摘要翻译：一种级联的Σ-Δ模数转换器（300），包括具有被配置为接收输入信号的输入的第一Σ-Δ调制器（310），第二Σ-Δ调制器（320），被配置为从第一调制器和噪声滤波器（230），被配置为从第一和第二调制器中的每一个接收输出信号，并提供调制和滤波的输出信号，其中模数转换器包括加法器（216），其被配置为提供误差信号从第一调制器通过组合来自第一调制器的环路滤波器（212）的输出信号与输入信号。

9. 发明申请

WO2010046853A2 SIGMA-DELTA MODULATOR 审中-公开
标题翻译： SIGMA-DELTA调制器
公开(公告)号：WO2010046853A2
公开(公告)日：2010-04-29
申请号：PCT/IB2009/054632
申请日：2009-10-21
申请人： NXP B.V. , BREEMS, Lucien, Johannes , VAN VELDHOVEN, Robert, Henrikus, Margaretha , RUTTEN, Robert
发明人： BREEMS, Lucien, Johannes , VAN VELDHOVEN, Robert, Henrikus, Margaretha , RUTTEN, Robert
CPC分类号： H03M3/414
摘要： A cascaded sigma-delta analog to digital converter (300) comprising a first sigma-delta modulator (310) having an input configured to receive an input signal, a second sigma-delta modulator (320) configured to receive an error signal from the first modulator and a noise filter (230) configured to receive an output signal from each of the first and second modulators and to provide a modulated and filtered output signal, wherein the analog to digital converter comprises an adder (216) configured to provide the error signal from the first modulator by combining an output signal from a loop filter (212) of the first modulator with the input signal.
摘要翻译：（300），其包括具有被配置为接收输入信号的输入的第一Σ-Δ调制器（310），被配置用于接收输入信号的第二Σ-Δ调制器（320）以接收来自所述第一调制器的误差信号和噪声滤波器（230），所述噪声滤波器（230）被配置为接收来自所述第一调制器和所述第二调制器中的每一个的输出信号并提供经调制和滤波的输出信号，其中所述模数转换器包括加法器 216），被配置为通过将来自第一调制器的环路滤波器（212）的输出信号与输入信号进行组合来提供来自第一调制器的误差信号。

10. 发明申请

WO2010013196A3 A METHOD TO LINEARIZE THE OUTPUT FROM AN ADC 审中-公开
标题翻译：一种从ADC中输出输出的方法
公开(公告)号：WO2010013196A3
公开(公告)日：2010-04-08
申请号：PCT/IB2009053273
申请日：2009-07-28
申请人： NXP BV , HEKSTRA ANDRIES PIETER , BREEMS LUCIEN JOHANNES , RUTTEN ROBERT
发明人： HEKSTRA ANDRIES PIETER , BREEMS LUCIEN JOHANNES , RUTTEN ROBERT
IPC分类号： H03M3/02
CPC分类号： H03M3/386 , H03M3/43 , H03M3/456
摘要： A method is disclosed of compensating the output of an ADC for non- linearity in the response of the ADC. The methodcomprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.
摘要翻译：公开了一种在ADC的响应中补偿ADC的输出以达到非线性的方法。该方法包括将模拟输入信号转换为未校正的数字ADC输出采样，将校正变量向量应用于未校正的ADC输出采样块中的每一个，以提供校正的ADC采样块，并且迭代地最小化测量的光谱平坦度校正的ADC样本的块对应于校正变量的向量。

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