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1. 发明申请

WO2010013196A2 A METHOD TO LINEARIZE THE OUTPUT FROM AN ADC 审中-公开
标题翻译：线性化来自ADC的输出的方法
公开(公告)号：WO2010013196A2
公开(公告)日：2010-02-04
申请号：PCT/IB2009/053273
申请日：2009-07-28
申请人： NXP B.V. , HEKSTRA,, Andries Pieter , BREEMS, Lucien Johannes , RUTTEN, Robert
发明人： HEKSTRA,, Andries Pieter , BREEMS, Lucien Johannes , RUTTEN, Robert
CPC分类号： H03M3/386 , H03M3/43 , H03M3/456
摘要： A method is disclosed of compensating the output of an ADC for non- linearity in the response of the ADC. The methodcomprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.
摘要翻译：公开了一种在ADC的响应中补偿ADC的输出以实现非线性的方法。该方法包括将模拟输入信号转换为未校正的数字ADC输出采样，将校正变量的矢量应用于未校正的ADC输出采样块中的每一个，以提供经校正的ADC采样块，以及迭代地最小化经校正的ADC采样块与对校正变量向量的响应。

2. 发明申请

WO2010046853A2 SIGMA-DELTA MODULATOR 审中-公开
标题翻译： SIGMA-DELTA调制器
公开(公告)号：WO2010046853A2
公开(公告)日：2010-04-29
申请号：PCT/IB2009/054632
申请日：2009-10-21
申请人： NXP B.V. , BREEMS, Lucien, Johannes , VAN VELDHOVEN, Robert, Henrikus, Margaretha , RUTTEN, Robert
发明人： BREEMS, Lucien, Johannes , VAN VELDHOVEN, Robert, Henrikus, Margaretha , RUTTEN, Robert
CPC分类号： H03M3/414
摘要： A cascaded sigma-delta analog to digital converter (300) comprising a first sigma-delta modulator (310) having an input configured to receive an input signal, a second sigma-delta modulator (320) configured to receive an error signal from the first modulator and a noise filter (230) configured to receive an output signal from each of the first and second modulators and to provide a modulated and filtered output signal, wherein the analog to digital converter comprises an adder (216) configured to provide the error signal from the first modulator by combining an output signal from a loop filter (212) of the first modulator with the input signal.
摘要翻译：（300），其包括具有被配置为接收输入信号的输入的第一Σ-Δ调制器（310），被配置用于接收输入信号的第二Σ-Δ调制器（320）以接收来自所述第一调制器的误差信号和噪声滤波器（230），所述噪声滤波器（230）被配置为接收来自所述第一调制器和所述第二调制器中的每一个的输出信号并提供经调制和滤波的输出信号，其中所述模数转换器包括加法器 216），被配置为通过将来自第一调制器的环路滤波器（212）的输出信号与输入信号进行组合来提供来自第一调制器的误差信号。

3. 发明申请

WO2010046859A1 SIGMA-DELTA MODULATOR 审中-公开
标题翻译： SIGMA-DELTA调制器
公开(公告)号：WO2010046859A1
公开(公告)日：2010-04-29
申请号：PCT/IB2009/054643
申请日：2009-10-21
申请人： NXP B.V. , VAN VELDHOVEN, Robert Henrikus Margaretha , BREEMS, Lucien Johannes , RUTTEN, Robert
发明人： VAN VELDHOVEN, Robert Henrikus Margaretha , BREEMS, Lucien Johannes , RUTTEN, Robert
IPC分类号： H03M3/00 , H03M1/06
CPC分类号： H03M3/368 , H03M3/436
摘要： A sigma-delta modulator (400) 400, 500, 600) for converting an input signal (X(s)) (X(s)) to a quantized output signal (Y(z)) (Y(z)), in which a feedback loop is provided between a filter (402) and a quantizer (403) of the modulator, the feedback loop configured to reduce quantization errors from the modulator by filtering and subtracting quantization noise fed back to an input of the quantizer (403).
摘要翻译：用于将输入信号（X（s））（X（s））转换为量化输出信号（Y（z））（Y（z））的Σ-Δ调制器（400）400,500,600）在调制器的滤波器（402）和量化器（403）之间提供反馈回路，反馈回路经配置以通过滤波和减去反馈给量化器（403）的输入的量化噪声来减少来自调制器的量化误差，。

4. 发明申请

WO2009062953A1 JITTER COMPENSATION 审中-公开
标题翻译：犹太人赔偿
公开(公告)号：WO2009062953A1
公开(公告)日：2009-05-22
申请号：PCT/EP2008/065381
申请日：2008-11-12
申请人： NXP B.V. , BREEMS, Lucien , RUTTEN, Robert , VAN VELDHOVEN, Robert Henrikus Margaretha
发明人： BREEMS, Lucien , RUTTEN, Robert , VAN VELDHOVEN, Robert Henrikus Margaretha
IPC分类号： H03D7/00 , H03M1/08 , H04B1/12
CPC分类号： H03D7/00 , H03M1/0836 , H03M1/12 , H03M3/372 , H03M3/458
摘要： The present invention relates to a circuit and a method for jitter compensation in a receiver system and for improving the SNR and/or the BER performance. The circuit for jitter compensation comprises: a combiner block (600) for combining a reference signal with an input signal (S in ) of said circuit (700, 900, 1000); a converter stage (605) for converting said input signal (S in ) together with said reference signal, said converter stage (605) being clocked by a clock signal modulated by a jitter signal; a forward path (631) having a first mixer unit (610) for multiplying a copy of an output signal (A) of said converter stage (605) with the frequency of said reference signal for generating a jitter compensating signal (B); and a compensation unit (608) for compensating jitter in said output signal (A) of said converter stage (605) in a direct output path (632) with said jitter compensating signal (B).
摘要翻译：本发明涉及用于接收机系统中的抖动补偿的电路和方法，并且用于提高SNR和/或BER性能。用于抖动补偿的电路包括：组合器块（600），用于将参考信号与所述电路（700,900,1000）的输入信号（Sin）组合; 用于将所述输入信号（Sin）与所述参考信号一起转换的转换器级（605），所述转换器级（605）由抖动信号调制的时钟信号计时; 具有用于将所述转换器级（605）的输出信号（A）的副本与所述参考信号的频率相乘以产生抖动补偿信号（B）的第一混频器单元（610）的前向通路（631）; 以及补偿单元（608），用于利用所述抖动补偿信号（B）在直接输出路径（632）中补偿所述转换器级（605）的所述输出信号（A）中的抖动。

5. 发明申请

WO2007113735A1 CALIBRATION CIRCUIT AND METHOD FOR A/D CONVERTER 审中-公开
标题翻译：校准电路和A / D转换器的方法
公开(公告)号：WO2007113735A1
公开(公告)日：2007-10-11
申请号：PCT/IB2007/051072
申请日：2007-03-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BREEMS, Lucien, J. , RUTTEN, Robert , VAN DER PLOEG, Hendrik
发明人： BREEMS, Lucien, J. , RUTTEN, Robert , VAN DER PLOEG, Hendrik
IPC分类号： H03M1/00
CPC分类号： H03M3/386 , H03M3/40 , H03M3/414
摘要： An analog to digital conversion circuit comprises a first digital noise cancellation filter (16) configured to provide a signal to cancel quantization noise from an analog to digital converted output signal. In a calibration phase a second digital noise cancellation filter (26) is has an input coupled to an input of the first digital noise cancellation filter (16). Mutually different sets of at least one-filter coefficients are programmed in the first and second digital noise canceling filters (16, 26). A difference is computed of averaged size indications of digital output signals derived using signals from the first and second digital noise cancellation filters (16, 26) using the same input signal. Updates of the sets of at least one filter coefficients are adapted dependent on the difference between the averaged size indications.
摘要翻译：模数转换电路包括第一数字噪声消除滤波器（16），其被配置为提供从模数转换输出信号消除量化噪声的信号。在校准阶段，第二数字噪声消除滤波器（26）具有耦合到第一数字噪声消除滤波器（16）的输入的输入。至少一个滤波器系数的相互不同的集合被编程在第一和第二数字噪声消除滤波器（16,26）中。使用相同的输入信号计算使用来自第一和第二数字噪声消除滤波器（16,26）的信号导出的数字输出信号的平均尺寸指示的差异。至少一个滤波器系数的集合的更新取决于平均尺寸指示之间的差异。

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