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    • 10. 发明申请
    • プログラマブルコントローラ
    • 可编程控制器
    • WO2002084421A1
    • 2002-10-24
    • PCT/JP2001/010179
    • 2001-11-21
    • 三菱電機株式会社藤原耕太郎宮部和明小林民樹城 友一
    • 藤原耕太郎宮部和明小林民樹城 友一
    • G05B19/05
    • G05B19/05G06F9/30145Y02P90/265
    • When an instruction code stored in a pipeline register (21d) is decoded by a decoding circuit (22a), it is judged, by decoding a device address, which device information on a RAM (11) or device information on a RAM (12) is used. If the device address designates the area of the RAM (12), the decoding circuit (22a) outputs a signal representing that the pipeline processing stop number is 0, unlike when the RAM (11) is designated. A pipeline register unit (21) does not outputs a signal representing that the pipeline stop signal is 1, so that the reading of the instruction code from the RAM (11) and the pipeline processing are not interrupted. As a result, a construction for executing a high-speed processing and a construction of a small size and a low price can be realized by a common hardware.
    • 当存储在流水线寄存器(21d)中的指令码由解码电路(22a)解码时,通过解码设备地址来判断RAM(11)上的哪个设备信息或RAM(12)上的设备信息, 用来。 如果设备地址指定RAM(12)的区域,则与指定RAM(11)不同,解码电路(22a)输出表示流水线处理停止号为0的信号。 流水线寄存器单元(21)不输出表示流水线停止信号为1的信号,从而不中断来自RAM(11)的指令代码的读取和流水线处理。 结果,可以通过普通硬件实现用于执行高速处理和小尺寸和低价格的构造。