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1. 发明申请

WO2010012970A1 INTERRUPT CONTROL FOR VIRTUAL PROCESSING APPARATUS 审中-公开
标题翻译：虚拟处理装置的中断控制
公开(公告)号：WO2010012970A1
公开(公告)日：2010-02-04
申请号：PCT/GB2009/001398
申请日：2009-06-03
申请人： ARM LIMITED , MANSELL, David, Hennah , GRISENTHWAITE, Richard, Roy
发明人： MANSELL, David, Hennah , GRISENTHWAITE, Richard, Roy
IPC分类号： G06F13/24 , G06F9/44
CPC分类号： G06F13/24 , G06F9/45558 , G06F9/4812
摘要： A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware (26) and virtual interface hardware (28). Hypervisor software responds to an interrupt received by the external interrupt interface hardware (26) to write data characterising that interrupt into list registers (18) of the virtual interface hardware (28). A guest operating system for the virtual machine of the virtual data processing apparatus being emulated may then read data from the virtual interface hardware (28) characterising the interrupt to be processed by that virtual machine. The virtual machine and the guest operating system interact with the virtual interface hardware (28) as if it were external interface hardware. The hypervisor software is responsible for maintaining the data within the virtual interface hardware (28) to properly reflect queued interrupts as received by the external interface (26).
摘要翻译：支持一个或多个虚拟处理装置的数据处理系统具有外部中断接口硬件（26）和虚拟接口硬件（28）。管理程序软件响应由外部中断接口硬件（26）接收的中断，以将表征该中断的数据写入虚拟接口硬件（28）的列表寄存器（18）。正在仿真的虚拟数据处理设备的虚拟机的客户操作系统然后可以从表征要由该虚拟机处理的中断的虚拟接口硬件（28）读取数据。虚拟机和客户机操作系统与虚拟接口硬件（28）进行交互，就像它是外部接口硬件一样。虚拟机管理程序软件负责维护虚拟接口硬件（28）内的数据以适当地反映由外部接口（26）接收的排队中断。

2. 发明申请

WO2009106788A1 INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE 审中-公开
标题翻译：具有错误维修和故障保修的集成电路
公开(公告)号：WO2009106788A1
公开(公告)日：2009-09-03
申请号：PCT/GB2008/004301
申请日：2008-12-29
申请人： ARM LIMITED , DAS, Shidhartha , BULL, David, Michael , ÖZER, Emre
发明人： DAS, Shidhartha , BULL, David, Michael , ÖZER, Emre
IPC分类号： G01R31/3181 , G06F11/10
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.
摘要翻译：集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。控制参数取决于电路内执行的处理。例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

3. 发明申请

WO2008007038A1 DATA DEPENDENCY SCOREBOARDING 审中-公开
标题翻译：数据依赖度分数
公开(公告)号：WO2008007038A1
公开(公告)日：2008-01-17
申请号：PCT/GB2006/002555
申请日：2006-07-11
申请人： ARM LIMITED , SYMES, Dominic, Hugo , REID, Alastair , FORD, Simon, Andrew
发明人： SYMES, Dominic, Hugo , REID, Alastair , FORD, Simon, Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/30036 , G06F9/345 , G06F9/3838
摘要： A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N- dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two- dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked.
摘要翻译：描述了一种并行处理技术，用于对保持状态数据的相应的N维记分板的数据元素的N维阵列执行并行处理操作。通过查看记分板内的相应状态值来执行数据元素N维数组内的数据元素的数据依赖性的危害检查。记分板内的给定数据元素的状态数据位于可从其N维阵列内的数据元素的位置导出的位置。因此，视频宏块的二维阵列可以具有相应的状态数据的二维记分板，该记分板指示各个宏块是否已经被解块或尚未被去块。

4. 发明申请

WO2007068865A1 INSTRUCTION ISSUE CONTROL WITHIN A MULTITHREADED PROCESSOR 审中-公开
标题翻译：在多处理器中的指令问题控制
公开(公告)号：WO2007068865A1
公开(公告)日：2007-06-21
申请号：PCT/GB2005/004859
申请日：2005-12-15
申请人： ARM LIMITED , MANSELL, David, Hennah , BILES, Stuart, David
发明人： MANSELL, David, Hennah , BILES, Stuart, David
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A multithreaded processor is provided with a saturating counter (40), which serves to generate a thread preference signal (36) to steer selection of which program thread operations are taken from for issue into the multiple processor pipelines. The counter (40) is updated based upon the selections made for issue. The counter is a saturating counter and its sign bit may be used as a thread preference signal when discriminating between two threads. The update made to the count value can be weighted depending upon programmable priorities associated with the respective threads as well as a weighting based upon the time taken to execute the type of operation selected.
摘要翻译：多线程处理器设置有饱和计数器（40），其用于产生线程偏好信号（36）以引导选择哪些程序线程操作被发送到多处理器管线。计数器（40）基于针对问题的选择而被更新。计数器是饱和计数器，并且当识别两个线程时，其符号位可以用作线程偏好信号。对计数值进行的更新可以根据与相应线程相关联的可编程优先级加权，以及基于执行所选择的操作类型所花费的时间的加权。

5. 发明申请

WO2006103381A1 SELECTING SUBROUTINE RETURN MECHANISMS 审中-公开
标题翻译：选择SUBRONTINE返回机制
公开(公告)号：WO2006103381A1
公开(公告)日：2006-10-05
申请号：PCT/GB2006/000331
申请日：2006-02-01
申请人： ARM LIMITED
发明人： GRISENTHWAITE, Richard, Roy , KIMELMAN, Paul , SEAL, David, James
IPC分类号： G06F9/40 , G06F9/32
CPC分类号： G06F9/3016 , G06F9/30054 , G06F9/322 , G06F9/4486
摘要： Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. Thus, the return address value can be used to invoke differing return instruction responses, such as an exception return response or a procedure return response. The one or more predetermined addresses may be conveniently allocated to the highest memory addresses within the memory map.
摘要翻译：在执行子程序之后，执行具有作为其输入操作数的地址的返回指令。将该输入操作数与一个或多个预定值进行比较以检测匹配，并且根据是否检测到匹配来选择返回指令响应。因此，返回地址值可以用于调用不同的返回指令响应，例如异常返回响应或过程返回响应。可以方便地将一个或多个预定地址分配给存储器映射中的最高存储器地址。

6. 发明申请

WO2005088441A2 INSERTING BITS WITHIN A DATA WORD 审中-公开
标题翻译：在数据字中插入位置
公开(公告)号：WO2005088441A2
公开(公告)日：2005-09-22
申请号：PCT/GB2004/003343
申请日：2004-08-03
申请人： ARM LIMITED
发明人： FORD, Simon, Andrew , CARPENTER, Paul, Matthew
IPC分类号： G06F9/315
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A data processing system (2) is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits within that destination value being unaltered.
摘要翻译：提供了一种数据处理系统（2），其支持移位和插入指令SLI，SRI，其用于将源数据值移位指定的移位量，然后将来自该移位值的移位值的位从插入位插入到目标值与该目标值内的其余位不变。

7. 发明申请

WO2004111834A2 DATA ACCESS PROGRAM INSTRUCTION ENCODING 审中-公开
标题翻译：数据访问程序指令编码
公开(公告)号：WO2004111834A2
公开(公告)日：2004-12-23
申请号：PCT/GB2003/005684
申请日：2003-12-30
申请人： ARM LIMITED
发明人： SEAL, David, James , VASEKIN, Vladimir
IPC分类号： G06F9/00
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/34 , G06F9/355
摘要： A data processing apparatus (2) is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilising a 12-bit offset field but with a fixed addressing mode and a second form utilising a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.
摘要翻译：提供了一种响应于数据访问指令执行数据访问操作的数据处理设备（2）。这些数据访问指令具有利用12位偏移场但具有固定寻址模式的第一形式，并且利用较短的8位偏移场，但具有在数据访问指令的操纵模式控制字段内指定的寻址模式的第二形式。

8. 发明申请

WO2004088504A1 CONTROLLING EXECUTION OF A BLOCK OF PROGRAM INSTRUCTIONS WITHIN A COMPUTER PROCESSING SYSTEM 审中-公开
标题翻译：控制计算机处理系统中程序指令块的执行
公开(公告)号：WO2004088504A1
公开(公告)日：2004-10-14
申请号：PCT/GB2003/005388
申请日：2003-12-11
申请人： ARM LIMITED
发明人： VASEKIN, Vladimir
IPC分类号： G06F9/32
CPC分类号： G06F9/3802 , G06F9/30054 , G06F9/324 , G06F9/3836
摘要： A data processing apparatus (2) is provided with an execute block instruction EMB which specifies a memory location of a block of program instructions to be executed as well as the length of that block of program instructions. When the end of that block of program instructions has been reached as tracked in response to the specified length value, a return to the main program flow is triggered. The instruction decoder (14) can include a block counter register (22) to keep track of the position within the block of program instructions being called. The block of program instructions are fetched by a prefetch unit (16) into the instruction pipeline (12) following the execute block instruction and are treated as having a program counter value corresponding to the execute block instruction whilst the block counter value keeps track of their separate positions within the block of program instructions.
摘要翻译：数据处理装置（2）具有指定要执行的程序指令块的存储器位置以及该程序指令块的长度的执行块指令EMB。当响应指定的长度值跟踪程序指令块的结束时，触发主程序流的返回。指令解码器（14）可以包括块计数器寄存器（22），以跟踪所调用的程序指令块内的位置。程序指令块由执行块指令之后由预取单元（16）读取到指令流水线（12）中，并且被视为具有与执行块指令相对应的程序计数器值，而块计数器值跟踪它们程序指令块内的单独位置。

9. 发明申请

WO2004063915A2 DATA PROCESSING PERFORMANCE CONTROL 审中-公开
标题翻译：数据处理性能控制
公开(公告)号：WO2004063915A2
公开(公告)日：2004-07-29
申请号：PCT/GB2003/004880
申请日：2003-11-10
申请人： ARM LIMITED
发明人： FLYNN, David, Walter
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/124 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A data processing system is provided having a processor (46) which generates control signals for controlling further circuits, such as a clock generator (4) and voltage controller (6), to operate so as to support a desired performance level of the processor. Whilst changing between performance levels, the further circuits are capable of supporting intermediate levels of operation and the processor exploits these by operating at those intermediate levels pending the final target level being reached.
摘要翻译：提供了一种具有处理器（46）的数据处理系统，该处理器生成用于控制另外的电路（例如时钟发生器（4）和电压控制器（6））进行操作以便支持处理器的期望性能水平。虽然在性能水平之间转换，但其他电路能够支持中间级别的操作，并且处理器通过在这些中间级别操作来利用这些级别，直到达到最终目标级别。

10. 发明申请

WO2004053685A1 INSTRUCTION TIMING CONTROL WITHIN A DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理系统中的指令时序控制
公开(公告)号：WO2004053685A1
公开(公告)日：2004-06-24
申请号：PCT/GB2003/004304
申请日：2003-10-06
申请人： ARM LIMITED , WATT, Simon, Charles
发明人： WATT, Simon, Charles
IPC分类号： G06F9/318
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： A data processing system (2) is provided which is responsive to program instructions that operate in a variable timing mode to require a variable number of processing cycles to complete. The system is also operable in a fixed timing mode, which may be programmable using a bit (or several bits) within a configuration controlling register, to operate in a fixed timing mode in which such instructions are forced to operate using a fixed number of processing cycles. Thus, suppression of instructions which fail their condition codes may be suppressed and early termination of program instructions similarly suppressed in a manner which helps resist an attack upon the security of the system by observing the number of processing cycles required to process certain data.
摘要翻译：提供了一种数据处理系统（2），其响应于以可变定时模式操作的程序指令，以要求完成可变数量的处理循环。该系统还可以在固定定时模式下操作，该定时模式可以使用配置控制寄存器内的位（或几位）来编程，以在固定的定时模式下操作，其中这些指令被迫使用固定数量的处理周期。因此，通过观察处理某些数据所需的处理周期的数量，可以抑制对条件码失败的指令的抑制和程序指令的提前终止以有助于抵抗系统的安全性的方式被抑制。

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