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1. 发明申请

WO2020047309A1 LOAD REDUCTION IN A VISUAL RENDERING SYSTEM 审中-公开
公开(公告)号：WO2020047309A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/048895
申请日：2019-08-29
申请人： QUALCOMM INCORPORATED
发明人： NIKHARA, Soman Ganesh , GUMMADI, Bapineedu Chowdary , VEERAMALLA, Pradeep , KADAMBALA, Ravi Shankar , CHOUDHA, Ankita Anil Kumar
IPC分类号： G06F3/01 , G06F1/16 , G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F1/3234
摘要： In one implementation, an electronic visual-rendering device includes an eye-tracking sensor and at least a first component. The eye-tracking sensor is configured to detect an eye-close event and, in response, output an eye-close-event message. The first component is configured to operate in at least a normal-power mode and a first low-power mode. The first components is configured to transition from operating in the normal-power mode to operating in the first low-power mode in response to the eye-tracking sensor's output of the eye-close-event message.

2. 发明申请

WO2020046844A1 METHOD, APPARATUS, AND SYSTEM FOR REDUCING PIPELINE STALLS DUE TO ADDRESS TRANSLATION MISSES 审中-公开
公开(公告)号：WO2020046844A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/048207
申请日：2019-08-26
申请人： QUALCOMM INCORPORATED
发明人： GHOSHAL, Pritha , CHOUDHARY, Niket , EIBL, Patrick , STEMPEL, Brian , RAY, David Scott , SPEIER, Thomas Philip
IPC分类号： G06F12/1027 , G06F9/38
摘要： A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

3. 发明申请

WO2019190767A1 USING MACHINE LEARNING TO OPTIMIZE MEMORY USAGE 审中-公开
公开(公告)号：WO2019190767A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/022316
申请日：2019-03-14
申请人： QUALCOMM INCORPORATED
发明人： JOHN, Dheebu Kaithavana
IPC分类号： G06F12/02 , G06F12/0862
摘要： Disclosed are methods and apparatuses for optimizing a usage of a memory storing apps. In an aspect, an apparatus receives time data reflecting when each of the apps in the memory was used, receives location data reflecting where each of the apps in the memory was used, receives frequency data reflecting a usage frequency of each of the apps in the memory and trains a neural network to learn an app usage pattern based on the received time data, received location data and received frequency data.

4. 发明申请

WO2013173721A1 AUDIO-VISUAL CONTENT DELIVERY 审中-公开
标题翻译：音视频内容传送
公开(公告)号：WO2013173721A1
公开(公告)日：2013-11-21
申请号：PCT/US2013/041603
申请日：2013-05-17
申请人： HOME BOX OFFICE, INC.
发明人： MUSSER,Jr., Elmer Gehman , EGGUM, Hardys Christ
IPC分类号： H04N21/222 , H04N21/2343 , H04N21/845
CPC分类号： H04N19/85 , H04N21/222 , H04N21/234354 , H04N21/23439 , H04N21/8456
摘要： In one embodiment, an edge server in a content-distribution network (CDN) stores a video asset in the form of partially encoded transport-stream chunks, where the partial encoding does not include quantization processing. When the edge server receives a request from a user device for a particular segment of the asset at a particular quality corresponding to a target bitrate, the edge server retrieves at least one partially encoded chunk corresponding to the request and completes the encoding (including quantization processing) of the at least one partially encoded chunk to generate an output file at the requested target bitrate. The edge server then adds corresponding audio data and any auxiliary data to the output file to generate a transport- stream file. The edge server then transmits the transport- stream to the user device as one or more transport- stream packets.
摘要翻译：在一个实施例中，内容分发网络（CDN）中的边缘服务器以部分编码的传输流块的形式存储视频资产，其中部分编码不包括量化处理。当边缘服务器以与目标比特率相对应的特定质量从用户设备接收对于资产的特定段的请求时，边缘服务器检索与该请求对应的至少一个部分编码的块，并完成编码（包括量化处理），以产生所请求的目标比特率的输出文件。然后，边缘服务器将相应的音频数据和任何辅助数据添加到输出文件以生成传输流文件。然后，边缘服务器将传输流作为一个或多个传输流分组传送到用户设备。

5. 发明申请

WO2020069239A1 EXPLOITING ACTIVATION SPARSITY IN DEEP NEURAL NETWORKS 审中-公开
公开(公告)号：WO2020069239A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/053325
申请日：2019-09-27
申请人： QUALCOMM INCORPORATED
发明人： HILL, Rexford , LAMB, Aaron , GOLDFARB, Michael , ANSARI, Amin , LOTT, Christopher
IPC分类号： G06N3/063
摘要： A method of exploiting activation sparsity in deep neural networks is described. The method includes retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The method also includes generating a compressed activation tensor comprising non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor. The method further includes processing the compressed activation tensor and the weight tensor to generate an output tensor.

6. 发明申请

WO2020046846A1 METHOD, APPARATUS, AND SYSTEM FOR PREFETCHING EXCLUSIVE CACHE COHERENCE STATE FOR STORE INSTRUCTIONS 审中-公开
公开(公告)号：WO2020046846A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/048209
申请日：2019-08-26
申请人： QUALCOMM INCORPORATED
发明人： YEN, Luke , CHOUDHARY, Niket , GHOSHAL, Pritha , SPEIER, Thomas Philip , STEMPEL, Brian Michael , MCAVOY, William James , EIBL, Patrick
IPC分类号： G06F12/0888 , G06F12/0817
摘要： A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

7. 发明申请

WO2019204101A1 PROVIDING INTERRUPT SERVICE ROUTINE (ISR) PREFETCHING IN MULTICORE PROCESSOR-BASED SYSTEMS 审中-公开
公开(公告)号：WO2019204101A1
公开(公告)日：2019-10-24
申请号：PCT/US2019/026839
申请日：2019-04-10
申请人： QUALCOMM INCORPORATED
发明人： SRINIVAS, Raghavendra , ROYCHOWDHURY, Kaustav , HALAVARTHI MATH REVANA, Siddesh
IPC分类号： G06F9/48 , G06F9/50
摘要： Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

8. 发明申请

WO2019125836A1 SYSTEM AND METHOD OF PRIORITY-BASED INTERRUPT STEERING 审中-公开
公开(公告)号：WO2019125836A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/065035
申请日：2018-12-11
申请人： QUALCOMM INCORPORATED
发明人： PLONDKE, Erich , VENKUMAHANTI, Suresh Kumar , WANG, Lin , CODRESCU, Lucian
IPC分类号： G06F9/48
CPC分类号： G06F9/4818 , G06F9/4812 , G06F9/4881
摘要： A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.

9. 发明申请

WO2014149358A1 INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION 审中-公开
标题翻译：交互式多路数字功率放大
公开(公告)号：WO2014149358A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/017651
申请日：2014-02-21
申请人： LSI Technologies Inc.
发明人： KISS, Peter , ABDELLI, Said, E. , LATURELL, Donald, R. , WILSON, Ross, S. , MACDONALD, James, F.
IPC分类号： H04L27/02 , H03M3/00 , H03F3/217 , H03H17/00 , H03H17/02
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit- stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit- stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit- stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit- stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
摘要翻译：在一个实施例中，射频发射机的功率放大系统包括数字信号源，该数字信号源向交织的比特流发生器提供数字输入信号，该数字信号源将数字切换信号输出到开关功率放大器。交错比特流发生器具有八路交织架构，有助于降低交错比特流发生器的有效时钟速率要求。交错比特流生成器包括用于接收数字输入信号并且将八个分数延迟的数字输出信号输出到比特流生成阵列的分数延迟滤波器阵列，其适于将八个对应的比特流输出到串行化器块，将八个比特流组合成数字切换信号。可以调整交错信号的相对相位以实现某些期望的效果。

10. 发明申请

WO2020046845A1 METHOD, APPARATUS, AND SYSTEM FOR MEMORY BANDWIDTH AWARE DATA PREFETCHING 审中-公开
公开(公告)号：WO2020046845A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/048208
申请日：2019-08-26
申请人： QUALCOMM INCORPORATED
发明人： CHOUDHARY, Niket , RAY, David Scott , SPEIER, Thomas Philip , ROBINSON, Eric , CAIN, Harold Wade III , SHARMA, Nikhil Narendradev , MCDONALD, Joseph Gerald , STEMPEL, Brian Michael , DRAPALA, Garrett Michael
IPC分类号： G06F12/0862
摘要： An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

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