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1. 发明申请

WO2023009247A1 DRAM CIRCUITRY AND METHOD OF FORMING DRAM CIRCUITRY 审中-公开
公开(公告)号：WO2023009247A1
公开(公告)日：2023-02-02
申请号：PCT/US2022/034440
申请日：2022-06-22
申请人： MICRON TECHNOLOGY, INC.
发明人： MIYASHITA, Toshihiko , MOCUTA, Dan
IPC分类号： H01L27/108 , H01L27/092 , H01L29/78
摘要： DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device, The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge¬ storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one ooff the wordlines aanndd comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET. The sense-line- amplifier transistors and the wordline-driver transistors individually comprise two source/drain regions that individually comprise conductively- doped epitaxial semiconductor material that is adjacent one of two laterally- opposing sides of the at least one fin in a vertical cross-section. Methods are also disclosed.

2. 发明申请

WO2022115227A1 AN ARRAY OF MEMORY CELLS, METHODS USED IN FORMING AN ARRAY OF MEMORY CELLS, METHODS USED IN FORMING AN ARRAY OF VERTICAL TRANSISTORS, METHODS USED IN FORMING AN ARRAY OF VERTICAL TRANSISTORS, AND METHODS USED IN FORMING AN ARRAY OF CAPACITORS 审中-公开
公开(公告)号：WO2022115227A1
公开(公告)日：2022-06-02
申请号：PCT/US2021/058427
申请日：2021-11-08
申请人： MICRON TECHNOLOGY, INC.
发明人： RIGANO, Antonino
IPC分类号： H01L27/108
摘要： A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

3. 发明申请

WO2021113046A1 A FERROELECTRIC CAPACITOR, A FERROELECTRIC MEMORY CELL, AN ARRAY OF FERROELECTRIC MEMORY CELLS, AND A METHOD OF FORMING A FERROELECTRIC CAPACITOR 审中-公开
公开(公告)号：WO2021113046A1
公开(公告)日：2021-06-10
申请号：PCT/US2020/060109
申请日：2020-11-12
申请人： MICRON TECHNOLOGY, INC.
发明人： JACOB, Clement , ANTONOV, Vassil, N. , GOSWAMI, Jaydeb , LIAO, Albert , PETZ, Christopher, W. , RAMASWAMY, Durai Vishak Nirmal
IPC分类号： H01L49/02 , H01L27/11502
摘要： A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where "M" is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.

4. 发明申请

WO2021096592A1 MEMORY ARRAYS AND METHODS USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS 审中-公开
公开(公告)号：WO2021096592A1
公开(公告)日：2021-05-20
申请号：PCT/US2020/050949
申请日：2020-09-16
申请人： MICRON TECHNOLOGY, INC.
发明人： KONG, Lingyu , DAYCOCK, David , KURAPATI, Venkata, Satyanarayana, Murthy , WIBOWO, Leroy, Ekarista
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： A method used in forming a memory array comprises forming a stack comprising vertically- alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material. Other aspects, including structure independent of method, are disclosed.

5. 发明申请

WO2021030078A1 TRANSISTOR AND METHODS OF FORMING TRANSISTORS 审中-公开
公开(公告)号：WO2021030078A1
公开(公告)日：2021-02-18
申请号：PCT/US2020/044509
申请日：2020-07-31
申请人： MICRON TECHNOLOGY, INC.
发明人： NAHAR, Manuj , MUTCH, Michael
IPC分类号： H01L29/78 , H01L29/10 , H01L29/08 , H01L29/423 , H01L29/66 , H01L21/268
摘要： A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately- adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately- above the internal interface physically contact at least some of the crystal grains that are immediately- below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately -above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately -above the internal interface is lower than immediately-below the internal interface and (b): a laterally -discontinuous insulative oxide. Other embodiments, including method, are disclosed.

6. 发明申请

WO2019240846A1 METHODS OF SEALING OPENINGS, AND METHODS OF FORMING INTEGRATED ASSEMBLIES 审中-公开
公开(公告)号：WO2019240846A1
公开(公告)日：2019-12-19
申请号：PCT/US2019/016695
申请日：2019-02-05
申请人： MICRON TECHNOLOGY, INC.
发明人： YANG, Guangjun
IPC分类号： H01L23/48 , H01L23/31 , H01L23/29 , H01L27/108
摘要： Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.

7. 发明申请

WO2019203896A1 INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES 审中-公开
公开(公告)号：WO2019203896A1
公开(公告)日：2019-10-24
申请号：PCT/US2018/060986
申请日：2018-11-14
申请人： MICRON TECHNOLOGY, INC.
发明人： UJIHARA, Shingo , TAKETANI, Hiroaki
IPC分类号： H01L27/108
摘要： Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.

8. 发明申请

WO2019133288A1 RECESSED ACCESS DEVICES AND DRAM CONSTRUCTIONS 审中-公开
公开(公告)号：WO2019133288A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/065633
申请日：2018-12-14
申请人： MICRON TECHNOLOGY, INC.
发明人： GAO, Yunfei , HILL, Richard, J. , SANDHU, Gurtej, S. , LIU, Haitao , PANDEY, Deepak, Chandra , PULUGURTHA, Srinivas , KARDA, Kamal, M.
IPC分类号： H01L27/108
摘要： A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.

9. 发明申请

WO2019133220A1 ASSEMBLIES CONTAINING PMOS DECKS VERTICALLY-INTEGRATED WITH NMOS DECKS, AND METHODS OF FORMING INTEGRATED ASSEMBLIES 审中-公开
公开(公告)号：WO2019133220A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/064411
申请日：2018-12-07
申请人： MICRON TECHNOLOGY, INC.
发明人： SILLS, Scott E. , BEIGEL, Kurt D.
IPC分类号： H01L27/092
摘要： Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.

10. 发明申请

WO2019133219A1 MEMORY CELLS, MEMORY ARRAYS, AND METHODS OF FORMING MEMORY ARRAYS 审中-公开
公开(公告)号：WO2019133219A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/064401
申请日：2018-12-07
申请人： MICRON TECHNOLOGY, INC.
发明人： KIM, Changhan
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11582
摘要： Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge- storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

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