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1. 发明申请

WO2013188705A3 A VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A UNIFIED STRUCTURE 审中-公开
公开(公告)号：WO2013188705A3
公开(公告)日：2013-12-19
申请号：PCT/US2013/045734
申请日：2013-06-13
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/38
摘要： An out of order processor. The processor includes a virtual load store queue for allocating a plurality of loads and a plurality of stores, wherein more loads and more stores can be accommodated beyond an actual physical size of the load store queue of the processor; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.

2. 发明申请

WO2013188696A3 AN INSTRUCTION DEFINITION TO IMPLEMENT LOAD STORE REORDERING AND OPTIMIZATION 审中-公开
公开(公告)号：WO2013188696A3
公开(公告)日：2013-12-19
申请号：PCT/US2013/045722
申请日：2013-06-13
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad , WOODS, Gregory, A.
发明人： ABDALLAH, Mohammad , WOODS, Gregory, A.
IPC分类号： G06F9/46 , G06F9/38
摘要： A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions, and of said sequence of instructions, splitting store instructions into a store address instruction and a store data instruction, wherein the store address performs address calculation and fetch, and wherein the store data performs a load of register contents to a memory address. The method further includes, of said sequence of instructions, splitting load instructions into a load address instruction and a load data instruction, wherein the load address performs address calculation and fetch, and wherein the load data performs a load of memory address contents into a register, and reordering the store address and load address instructions earlier and further away from LD/SD the instruction sequence to enable earlier dispatch and execution of the loads and the stores.

3. 发明申请

WO2013188460A2 A VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A DISTRIBUTED STRUCTURE 审中-公开
标题翻译：具有分布式结构的动态分配窗口的虚拟装载商店
公开(公告)号：WO2013188460A2
公开(公告)日：2013-12-19
申请号：PCT/US2013/045261
申请日：2013-06-11
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
CPC分类号： G06F9/3836 , G06F5/14 , G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3851 , G06F9/3855 , G06F2205/063 , G06F2205/064
摘要： An out of order processor. The processor includes a distributed load queue and a distributed store queue that maintain single program sequential semantics while allowing an out of order dispatch of loads and stores across a plurality of cores and memory fragments; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.
摘要翻译：一个乱序处理器。处理器包括分布式负载队列和分布式存储队列，其维护单个程序顺序语义，同时允许跨多个核心和存储器片段的负载和存储的乱序分派; 其中所述处理器除了加载和存储之外分配超出所述加载/存储队列的实际物理大小限制的其他指令; 并且其中即使中间加载或存储在加载存储队列中没有空格，也可以调度和执行其他指令。

4. 发明申请

WO2013188414A2 A METHOD AND SYSTEM FOR FILTERING THE STORES TO PREVENT ALL STORES FROM HAVING TO SNOOP CHECK AGAINST ALL WORDS OF A CACHE 审中-公开
标题翻译：一种用于过滤存储的方法和系统，以防止所有存储器对所有字段的高速缓存进行SNOOP检查
公开(公告)号：WO2013188414A2
公开(公告)日：2013-12-19
申请号：PCT/US2013/045193
申请日：2013-06-11
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
CPC分类号： G06F12/0831 , G06F9/30047 , G06F9/3834 , G06F12/0862 , G06F2212/6028 , G06F2212/621
摘要： In a processor, a method for filtering stores to prevent all stores from having to snoop check against all words of a cache. The method includes implementing a cache wherein stores snoop the caches for address matches to maintain coherency; marking a portion of a cache line if a given core out of a plurality of cores loads from that portion by using an access mask; checking the access mask upon execution of subsequent stores to the cache line; and causing a miss prediction when a subsequent store to the portion of the cache line sees a prior mark from a load in the access mask.
摘要翻译：在处理器中，用于过滤存储的方法，以防止所有商店必须窥探高速缓存的所有字。该方法包括实现高速缓存，其中存储窥探用于地址匹配的高速缓存以维持一致性; 如果多个核心中的给定核心通过使用访问掩码从该部分加载，则标记高速缓存行的一部分; 在将后续存储执行到高速缓存行时检查访问掩码; 并且当对高速缓存行的部分的后续存储看到来自访问掩码中的加载的先前标记时，引起未命中预测。

5. 发明申请

WO2013188311A1 A LOAD STORE BUFFER AGNOSTIC TO THREADS IMPLEMENTING FORWARDING FROM DIFFERENT THREADS BASED ON STORE SENIORITY 审中-公开
标题翻译：基于存储优先级的负载存储缓冲器对不同螺纹的螺纹执行螺纹
公开(公告)号：WO2013188311A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/045020
申请日：2013-06-10
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30047 , G06F9/3009 , G06F9/3017 , G06F9/3826 , G06F9/3834 , G06F9/3851 , G06F12/1425 , G06F2212/1052
摘要： In a processor, a thread agnostic unified store queue and a unified load queue method for out of order loads in a memory consistency model using shared memory resources. The method includes implementing a memory resource that can be accessed by a plurality of asynchronous cores, wherein the plurality of cores share a unified store queue and a unified load queue; and implementing an access mask that functions by tracking which words of a cache line are accessed via a load, wherein the cache line includes the memory resource, wherein the load sets a mask bit within the access mask when accessing a word of the cache line, and wherein the mask bit blocks accesses from other loads from a plurality of cores. The method further includes checking the access mask upon execution of subsequent stores from the plurality of cores to the cache line, wherein stores from different threads can forward to loads of different threads while still maintaining in order memory consistency semantics; and causing a miss prediction when a subsequent store to the portion of the cache line sees a prior mark from a load in the access mask, wherein the subsequent store will signal a load queue entry corresponding to that load by using a tracker register and a thread ID register.
摘要翻译：在处理器中，线程不可知统一存储队列和统一的加载队列方法，用于使用共享内存资源在内存一致性模型中进行乱序加载。该方法包括实现可由多个异步核心访问的存储器资源，其中所述多个核共享统一存储队列和统一加载队列; 以及实现通过跟踪通过负载访问高速缓存行的哪些字的功能的访问掩码，其中所述高速缓存行包括所述存储器资源，其中当访问所述高速缓存行的字时，所述负载设置所述访问掩码内的掩码位，并且其中所述掩码位阻止来自多个核的其它负载的访问。该方法还包括：在执行从多个核到高速缓存行的后续存储时检查访问掩码，其中来自不同线程的存储可以转发到不同线程的负载，同时仍然按照存储器一致性语义进行维护; 并且当对所述高速缓存行的所述部分的后续存储看到来自所述访问掩码中的负载的先前标记时，导致未命中预测，其中所述后续存储将通过使用跟踪器寄存器和线程来发出与所述负载相对应的加载队列条目 ID寄存器。

6. 发明申请

WO2013089786A8 CACHE REPLACEMENT POLICY 审中-公开
公开(公告)号：WO2013089786A8
公开(公告)日：2013-06-20
申请号：PCT/US2011/065584
申请日：2011-12-16
申请人： SOFT MACHINES, INC. , AVUDAIYAPPAN, Karthikeyan , ABDALLAH, Mohammad
发明人： AVUDAIYAPPAN, Karthikeyan , ABDALLAH, Mohammad
IPC分类号： G06F12/08
摘要： Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue cache requests that miss a second cache after missing a first cache. The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache. The apparatus may be further configured to lock the evict way recorded in the additional memory, for example, to prevent reuse of the evict way. The apparatus may be further configured to unlock the evict way responsive to a fill from the second cache to the cache. The additional memory may be a component of a higher level cache.

7. 发明申请

WO2012135041A2 REGISTER FILE SEGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES 审中-公开
标题翻译：通过使用由可分离引擎监视的虚拟指令来支持代码块执行的注册文件部分
公开(公告)号：WO2012135041A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/030383
申请日：2012-03-23
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/46 , G06F9/30 , G06F12/08
CPC分类号： G06F9/5077 , G06F9/30043 , G06F9/30123 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/5016 , G06F9/505 , G06F12/0848 , G06F13/1657 , G06F2212/282
摘要： A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.
摘要翻译：一种用于使用用于处理器的多个寄存器文件段来执行指令的系统。该系统包括用于接收输入指令序列的全局前端调度器，其中全局前端调度器将输入指令序列划分为指令的多个代码块，并且生成描述代码块指令之间相互依赖关系的多个继承向量。该系统还包括处理器的多个虚拟核心，其耦合以接收由全局前端调度器分配的代码块，其中每个虚拟核心包括多个可分区引擎的相应资源子集，其中通过使用根据虚拟核心模式并根据各自的继承向量的可分割引擎。多个寄存器文件段被耦合到可分割引擎以提供数据存储。

8. 发明申请

WO2012106471A1 MULTIVOLTAGE CLOCK SYNCHRONIZATION 审中-公开
标题翻译：多媒体时钟同步
公开(公告)号：WO2012106471A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023545
申请日：2012-02-01
申请人： SYNOPSYS, INC. , FERREIRA DE FIGUEIREDO, Pedro, Miguel
发明人： FERREIRA DE FIGUEIREDO, Pedro, Miguel
IPC分类号： H03K19/096
CPC分类号： G06F1/10
摘要： A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal.
摘要翻译：公开了一种电平转换器电路。电平转换器电路包括产生第一输出信号的第一电平转换器和产生第二输出信号的第二电平转换器。电平转换器电路还包括耦合到第一电平转换器的边沿选择器和选择第一输出信号或第二输出信号的上升沿的第二电平转换器，并且选择第一输出信号或第二输出信号，以产生优化的输出信号。

9. 发明申请

WO2012051262A2 AN INSTRUCTION SEQUENCE BUFFER TO ENHANCE BRANCH PREDICTION EFFICIENCY 审中-公开
标题翻译：一种提高分支预测效率的指令序列缓冲器
公开(公告)号：WO2012051262A2
公开(公告)日：2012-04-19
申请号：PCT/US2011/055917
申请日：2011-10-12
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/06 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30058 , G06F9/3808 , G06F9/3844
摘要： A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.
摘要翻译：
用于输出替代指令序列的方法。该方法包括跟踪重复命中以确定用于微处理器的一组频繁命中的指令序列。识别频繁错失预测的分支指令，其中分支指令的预测结果经常是错误的。分支指令目标的替代指令序列被存储到缓冲器中。在分支指令的预测结果错误的分支指令的后续命中时，从缓冲器输出替代指令序列。

10. 发明申请

WO2011103117A1 VERSATILE KEYBOARD INPUT AND OUTPUT DEVICE 审中-公开
标题翻译：多功能键盘输入和输出设备
公开(公告)号：WO2011103117A1
公开(公告)日：2011-08-25
申请号：PCT/US2011/024976
申请日：2011-02-16
申请人： PANASONIC CORPORATION OF NORTH AMERICA , MYERS, Stephen , RIGAZIO, Luca
发明人： MYERS, Stephen , RIGAZIO, Luca
IPC分类号： G06F3/02
CPC分类号： G06F3/0238 , A63F13/23 , A63F13/285 , G06F3/016 , G06F3/0202 , G06F3/044 , H01H13/83 , H01H2003/0293 , H01H2215/004 , H03K17/9622 , H03K2217/96062
摘要： A versatile keyboard input and output device is described. The keyboard device includes a housing having a plurality of buttons, with each button individually clickable, and a capacitive sensing element under each button for touch sensing. The versatile keyboard input and output device further includes a lighting element under each button to provide selective lighting for each button, and a plurality of button glyphs for the plurality of buttons respectively, wherein the button glyphs are selectively visually changeable. The keyboard input device also includes a haptic feedback mechanism included in the housing for providing haptic feedback for the plurality of buttons.
摘要翻译：描述了通用的键盘输入和输出设备。键盘装置包括具有多个按钮的壳体，其中每个按钮可单独地点击，以及每个按钮下的用于触摸感测的电容感测元件。多功能键盘输入和输出设备还包括在每个按钮下方的照明元件，以分别为每个按钮提供选择性照明，以及多个按钮字形，用于多个按钮，其中按钮字形被选择性地视觉上可变化。键盘输入装置还包括包含在外壳中的触觉反馈机构，用于为多个按钮提供触觉反馈。

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