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1. 发明申请

WO1997016792A1 VIRTUAL MAINTENANCE NETWORK IN MULTIPROCESSING SYSTEM 审中-公开
标题翻译：虚拟维护网络在多处理系统中的应用
公开(公告)号：WO1997016792A1
公开(公告)日：1997-05-09
申请号：PCT/US1996015117
申请日：1996-09-23
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , THORSON, Gregory, M.
IPC分类号： G06F15/163
CPC分类号： G06F15/17337
摘要： A multiprocessor computer system includes processing element nodes interconnected with physical communication links in an n-dimensional topology. A flow controlled virtual channel has virtual channel buffers assigned to each physical communication link to store packets containing information to be transferred between the processing element nodes. A non-flow controlled virtual maintenance channel has maintenance channel buffers assigned to each physical communication link to store packets of maintenance information to be transferred between the processing element nodes. The virtual maintenance channel is assigned a higher priority for accessing the physical communication links than the flow controlled virtual channel.
摘要翻译：多处理器计算机系统包括与n维拓扑中的物理通信链路互连的处理元件节点。流控虚拟通道具有分配给每个物理通信链路的虚拟通道缓冲器，以存储包含要在处理元件节点之间传送的信息的分组。非流控制的虚拟维护通道具有分配给每个物理通信链路的维护通道缓冲器，以存储要在处理元件节点之间传送的维护信息的分组。虚拟维护通道被分配了比流量控制的虚拟通道更高的访问物理通信链路的优先级。

2. 发明申请

WO1993012487A1 INPUT/OUTPUT SUBSYSTEM FOR THE MULTI-PROCESSOR 审中-公开
标题翻译：多处理器的输入/输出子系统
公开(公告)号：WO1993012487A1
公开(公告)日：1993-06-24
申请号：PCT/US1992010208
申请日：1992-11-24
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , BENZSCHAWAL, Gary, E. , HEIDTKE, Lonnie, R. , CHEN, Steven, S. , SIMMONS, Fredrich, J. , SPIX, George, A.
IPC分类号： G06F13/40
CPC分类号： G06F13/122 , G06F13/362 , G06F13/4022
摘要： Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory. Direct memory access requests are queued at the channel while higher-priority serial transfer requests are serviced. Direct memory access is provided in 64-word blocks designated by perimeter packets indicating a number of blocks, starting address in main memory, starting address in solid state memory, and an indication of the direction of transfer.
摘要翻译：每个16个CPU的四个簇分别与固态存储器和主存储器相关联。每个CPU与与将相关联的CPU互连到串行端口的信道仲裁器唯一相关联。每个信道仲裁器与一组16个串行信道相关联。每个串行通道又互连到通道适配器，该通道适配器包括适于与特定外围设备进行交互的软件和固件。每个通道适配器还具有与设备无关的软件和固件，用于与信道仲裁器的数据传输。信道仲裁器包括用于通过CPU访问主存储器的存储器端口，用于接受服务请求并向CPU提供中断的端口，直接存储器访问控制逻辑，仲裁控制逻辑，与通道适配器相关联的串行端口以及并行端口与固态存储器相关联。直接存储器访问请求在通道排队，而优先级较高的串行传输请求被服务。在由周边数据包指定的64个字块中提供直接存储器访问，指示块的数量，主存储器中的起始地址，固态存储器中的起始地址以及传输方向的指示。

3. 发明申请

WO1991009423A1 IMPROVED REDUCED CAPACITANCE CHIP CARRIER 审中-公开
标题翻译：改进的减少电容芯片载体
公开(公告)号：WO1991009423A1
公开(公告)日：1991-06-27
申请号：PCT/US1990007097
申请日：1990-12-04
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , EBERLEIN, Delvin, D.
IPC分类号： H01L23/64
CPC分类号： H01L23/49861 , H01L23/13 , H01L23/147 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit chip carrier having reduced and predictable interlead capacitance, reduced glass chip formation, and improved wirebonding characteristics is disclosed. The chip carrier includes a substrate (201) having a central cavity (106) for locating an integrated circuit die, an inner channel (202) and an outer channel (203), adhesive glass (105) located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads (107) embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass (104) extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.
摘要翻译：公开了一种具有减少且可预测的交错电容，降低的玻璃芯片形成和改善引线接合特性的集成电路芯片载体。芯片载体包括具有用于定位集成电路芯片的中心腔（106），内部通道（202）和外部通道（203）的基底（201），粘合剂玻璃（105）位于通道中并溢出衬底表面，安装在衬底上的引线框架，其具有嵌入在粘合剂玻璃中的多个引线（107），其溢出并且共面地搁置在衬底上，引线从衬底外周向内延伸到腔边缘附近，以及薄层密封玻璃（104），其在所述外部通道上从所述基板的周边延伸，以密封所述芯片载体。

4. 发明申请

WO1990013143A1 METALLIZED WAFER-SHAPED SUBSTRATE CHIP CARRIERS 审中-公开
标题翻译：金属化的波形基板芯片载体
公开(公告)号：WO1990013143A1
公开(公告)日：1990-11-01
申请号：PCT/US1990002179
申请日：1990-04-20
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , STEITZ, Richard, R. , CHRISTIE, Diane, M. , NEUMANN, Eugene, F. , AUGUST, Melvin, C. , NELSON, Stephen
IPC分类号： H01L23/13
CPC分类号： H01L23/13 , H01L21/4846 , H01L23/49866 , H01L23/5386 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates (10) is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces (28) can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogenous for a portion of the trace. One metal portion of the traces is of a type compatible with an IC chip (30) placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

5. 发明申请

WO1996032681A1 ADAPTIVE ROUTING MECHANISM FOR TORUS INTERCONNECTION NETWORK 审中-公开
标题翻译：用于多功能互联网络的自适应路由机制
公开(公告)号：WO1996032681A1
公开(公告)日：1996-10-17
申请号：PCT/US1995015483
申请日：1995-11-29
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , THORSON, Gregory, M. , SCOTT, Steven, L.
IPC分类号： G06F15/16
CPC分类号： G06F15/17331 , G06F15/17381
摘要： A routing mechanism includes two acyclic non-adaptive virtual channels having two types of virtual channel buffers to store packets along deterministic virtual paths between nodes in an n-dimensional networked system, and an adaptive virtual channel having a third type of virtual channel buffer to store the packets along non-deterministic virtual paths between the nodes. The packets are routed between the nodes along either selected portions of the deterministic virtual paths or selected portions of the non-deterministic virtual paths based on routing information such that a packet is never routed on a selected portion of one of the non-deterministic virtual paths unless the third type virtual channel buffer associated with the selected portion of the one non-deterministic virtual path has sufficient space available to store the entire packet.
摘要翻译：路由机制包括两个非循环非自适应虚拟信道，其具有两种类型的虚拟信道缓冲器，用于沿着n维网络系统中的节点之间的确定性虚拟路径存储分组，以及具有第三类型的虚拟信道缓冲器以存储的自适应虚拟信道节点之间的非确定性虚拟路径的数据包。基于路由信息，分组沿着确定性虚拟路径的所选部分或非确定性虚拟路径的选定部分在节点之间路由，使得分组绝不在非确定性虚拟路径之一的选定部分上路由除非与所述一个非确定性虚拟路径的所选部分相关联的第三类型虚拟通道缓冲器具有足够的可用于存储整个分组的空间。

6. 发明申请

WO1994006076A1 HIGH PERFORMANCE MANTISSA DIVIDER 审中-公开
标题翻译：高性能MANTISSA DIVIDER
公开(公告)号：WO1994006076A1
公开(公告)日：1994-03-17
申请号：PCT/US1993007192
申请日：1993-07-26
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , SMITH, James, E.
IPC分类号： G06F07/52
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49947 , G06F7/5375
摘要： A high performance floating point mantissa divider employs SRT division, a Radix-4 redundant digit set and the principles of carry-save addition. At each step in the division, the upper few most significant bits of the partial remainder and the divisor are inspected via a look-up table to select the appropriate quotient digits. The quotient digits are represented in a Radix-4 redundant digit set, and the look-up table is generated using SRT division principles. The selected quotient digit is used to control a multiplexor which selects the selected multiple of the divisor. This value is substracted from the partial remainder via a carry-save adder to form the new partial remainder. As the quotient digits are generated, they are placed in two shift registers, one for the sum digits and one for carry digits. When the division is complete, the shift registers are added to give the final quotient mantissa. A combination of a carry save adder and carry lookahead adder reduce the practical implementation to only 8 logic levels.
摘要翻译：高性能浮点尾数分频器采用SRT除法，基数4冗余数字集和进位保存加法原理。在除法中的每个步骤，部分余数和除数的最高几个最高有效位通过查找表进行检查，以选择适当的商数。商数字用基数-4冗余数字集表示，并且使用SRT分割原则生成查找表。所选择的商数用于控制选择除数的选定倍数的多路复用器。该值通过进位保存加法器从部分余数中减去以形成新的部分余数。由于产生商数，它们被放置在两个移位寄存器中，一个用于和位数字，一个用于进位数字。当分割完成时，添加移位寄存器以给出最终的商数尾数。进位存储加法器和进位先行加法器的组合将实际实现减少到仅8个逻辑电平。

7. 发明申请

WO1992015071A1 TWO PIPE OPERATION IN VECTOR PROCESSOR FOR MULTIPROCESSING SUPERCOMPUTER 审中-公开
标题翻译：用于多处理超级计算机的矢量处理器中的两个管道操作
公开(公告)号：WO1992015071A1
公开(公告)日：1992-09-03
申请号：PCT/US1991007378
申请日：1991-10-03
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , DAVIS, Lester, T. , FAANES, Gregory, J. , GUPTA, Ram, K. , HSIUNG, Christopher, C. , PASSINT, Randal, S. , PRIBNOW, Richard, D. , SCHIFFLEGER, Alan, J.
IPC分类号： G06F15/78
CPC分类号： G06F9/3885 , G06F15/8076 , G06F15/8092
摘要： Increased speed of execution of vector operations is achieved in a multiprocessing vector register supercomputer by intra-processor parallelism. Each processor contains two pipes interfacing the vector registers to dual fonctional units. Operands are simultaneously transmitted on the two pipes to one of the dual functional units. The dual functional unit performs an identical algorithm in parallel on each of the operands and simultaneously transmits the results back to the vector registers.
摘要翻译：通过内部处理器并行性在多处理向量寄存器超级计算机中实现向量运算速度的提高。每个处理器包含两个管道，将向量寄存器连接到双功能单元。操作数同时在两个管道上传输到双功能单元之一。双功能单元在每个操作数上并行执行相同的算法，并同时将结果发送回向量寄存器。

8. 发明申请

WO1992009968A1 VECTOR WORD SHIFT BY Vo SHIFT COUNT IN VECTOR SUPERCOMPUTER PROCESSOR 审中-公开
标题翻译： VECTOR WORD通过Vo SHIFT COUNT in VECTOR SUPERCOMPUTER PROCESSOR进行移位
公开(公告)号：WO1992009968A1
公开(公告)日：1992-06-11
申请号：PCT/US1991007360
申请日：1991-10-02
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , SCHIFFLEGER, Alan, J. , GUPTA, Ram, K. , HSUING, Christopher, C.
IPC分类号： G06F15/78
CPC分类号： G06F9/30032 , G06F9/30036 , G06F15/8076 , G06F15/8084
摘要： Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.
摘要翻译：在矢量超级计算机处理器中实现向量寄存器的向量寄存器的向量移位元件。第一个向量寄存器包含一组操作数，第二个向量寄存器包含一组移位计数，每个操作数一个移位计数。操作数和移位计数依次传送到向量移位功能单元，该单元将操作数移位一个等于移位计数值的量。移位的操作数存储在第三个向量寄存器中。矢量移位功能单元还实现了预定数量的矢量寄存器元件到另一向量寄存器的不同字位置的字移位。

9. 发明申请

WO1991008588A1 HIGH POWER, HIGH DENSITY INTERCONNECT METHOD AND APPARATUS FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：高功率，高密度互连方法和集成电路设备
公开(公告)号：WO1991008588A1
公开(公告)日：1991-06-13
申请号：PCT/US1990002586
申请日：1990-05-09
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , SHEPHERD, Lloyd, T. , AUGUST, Melvin , KRUCHOWSKI, James, N.
IPC分类号： H01L23/538
CPC分类号： H05K1/0265 , H01L21/4857 , H01L23/49866 , H01L23/50 , H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/162 , H05K1/167 , H05K3/388 , H05K3/421 , H05K3/422 , H05K3/4661 , H05K3/467 , H05K2201/0317 , H05K2201/0376 , H05K2201/09309 , H05K2203/0315 , H05K2203/0361 , H05K2203/072 , H05K2203/0733 , Y10S428/901 , Y10T428/24917 , H01L2924/00
摘要： The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-built electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive techniques. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits (22) can easily be supplied with their necessary power requirements.

10. 发明申请

WO1991003085A1 IMPROVED LASER DIODE PACKAGE 审中-公开
标题翻译：改进的激光二极管封装
公开(公告)号：WO1991003085A1
公开(公告)日：1991-03-07
申请号：PCT/US1990004175
申请日：1990-07-25
申请人： CRAY RESEARCH, INC.
发明人： CRAY RESEARCH, INC. , BAUSMAN, Marvin, D., Jr.
IPC分类号： H01S03/025
CPC分类号： H01S5/02212 , H01S5/02232 , H01S5/0243
摘要： A semiconductor mounting package (10) is provided which permits the active p-n junction (27) of a light emitting semiconductor (18) to be operated in a liquid heat transfer fluid (16). The package (10) provides optical coupling for extracting light energy.
摘要翻译：提供一种半导体安装封装（10），其允许发光半导体（18）的有源p-n结（27）在液体传热流体（16）中操作。封装（10）提供用于提取光能的光耦合。

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