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    • 1. 发明申请
    • INPUT/OUTPUT SUBSYSTEM FOR THE MULTI-PROCESSOR
    • 多处理器的输入/输出子系统
    • WO1993012487A1
    • 1993-06-24
    • PCT/US1992010208
    • 1992-11-24
    • CRAY RESEARCH, INC.
    • CRAY RESEARCH, INC.BENZSCHAWAL, Gary, E.HEIDTKE, Lonnie, R.CHEN, Steven, S.SIMMONS, Fredrich, J.SPIX, George, A.
    • G06F13/40
    • G06F13/122G06F13/362G06F13/4022
    • Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory. Direct memory access requests are queued at the channel while higher-priority serial transfer requests are serviced. Direct memory access is provided in 64-word blocks designated by perimeter packets indicating a number of blocks, starting address in main memory, starting address in solid state memory, and an indication of the direction of transfer.
    • 每个16个CPU的四个簇分别与固态存储器和主存储器相关联。 每个CPU与与将相关联的CPU互连到串行端口的信道仲裁器唯一相关联。 每个信道仲裁器与一组16个串行信道相关联。 每个串行通道又互连到通道适配器,该通道适配器包括适于与特定外围设备进行交互的软件和固件。 每个通道适配器还具有与设备无关的软件和固件,用于与信道仲裁器的数据传输。 信道仲裁器包括用于通过CPU访问主存储器的存储器端口,用于接受服务请求并向CPU提供中断的端口,直接存储器访问控制逻辑,仲裁控制逻辑,与通道适配器相关联的串行端口以及并行端口 与固态存储器相关联。 直接存储器访问请求在通道排队,而优先级较高的串行传输请求被服务。 在由周边数据包指定的64个字块中提供直接存储器访问,指示块的数量,主存储器中的起始地址,固态存储器中的起始地址以及传输方向的指示。